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81. 发明申请

US20120195591A1 DUAL NETWORK TYPES SOLUTION FOR COMPUTER INTERCONNECTS 有权
标题翻译：双网络类型计算机互连解决方案
公开(公告)号：US20120195591A1
公开(公告)日：2012-08-02
申请号：US13444762
申请日：2012-04-11
申请人： Alan Benner , Ramakrishnan Rajamony , Eugen Schenfeld , Craig Brian Stunkel , Peter A. Walker
发明人： Alan Benner , Ramakrishnan Rajamony , Eugen Schenfeld , Craig Brian Stunkel , Peter A. Walker
IPC分类号： H04L12/66 , H04J14/00
CPC分类号： H04L12/4641 , H04L12/28 , H04L12/66
摘要： A computing system includes: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously.
摘要翻译：计算系统包括：多个紧密耦合的处理节点; 使用电路交换模式的多个电路交换网络，互连处理节点，以及处理满足一个或多个标准的数据传输; 以及多个电子分组交换网络，其还互连处理节点，处理满足至少一个准则的数据传输。电路交换网络和电子分组交换网络同时工作。

82. 发明授权

US08230422B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08230422B2
公开(公告)日：2012-07-24
申请号：US11034546
申请日：2005-01-13
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F9/40 , G06F13/28
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

83. 发明授权

US08140759B2 Specifying an access hint for prefetching partial cache block data in a cache hierarchy 失效
标题翻译：指定用于在缓存层次结构中预取部分高速缓存块数据的访问提示
公开(公告)号：US08140759B2
公开(公告)日：2012-03-20
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

84. 发明申请

US20100268886A1 SPECIFYING AN ACCESS HINT FOR PREFETCHING PARTIAL CACHE BLOCK DATA IN A CACHE HIERARCHY 失效
标题翻译：指定访问提示用于缓存高速缓存中的部分缓存块数据
公开(公告)号：US20100268886A1
公开(公告)日：2010-10-21
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

85. 发明授权

US07409504B2 Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response 有权
标题翻译：链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行的顺序非均匀访问
公开(公告)号：US07409504B2
公开(公告)日：2008-08-05
申请号：US11245312
申请日：2005-10-06
申请人： Ramakrishnan Rajamony , Hazim Shafi , Derek Edward Williams , Kenneth Lee Wright
发明人： Ramakrishnan Rajamony , Hazim Shafi , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.
摘要翻译：一种用于在数据在第一耦合处理器的高速缓存中接收数据之前顺序耦合高速缓存行的连续处理器请求的方法。同质和非均匀的操作彼此链接，并且一致性协议包括与链接状态相关联的几个新的中间一致性响应。分配链接一致性状态以在第一处理器接收到数据之前跟踪处理器请求链和授予访问权限。链接的一致性状态还标识接收处理器的地址。当在链中的第一处理器的高速缓存处接收到数据时，处理器完成其对数据的（或与）数据的操作，然后将数据转发到链中的下一个处理器。链接的一致性协议通过减少重试次数来释放地址总线带宽。

86. 发明申请

US20080181111A1 OPTIMAL INTERCONNECT UTILIZATION IN A DATA PROCESSING NETWORK 失效
标题翻译：数据处理网络中的最佳互连应用
公开(公告)号：US20080181111A1
公开(公告)日：2008-07-31
申请号：US12059762
申请日：2008-03-31
申请人： Wesley Michael Felter , Orran Yaakov Krieger , Ramakrishnan Rajamony
发明人： Wesley Michael Felter , Orran Yaakov Krieger , Ramakrishnan Rajamony
IPC分类号： H04L12/56
CPC分类号： H04L43/00 , H04L41/0896 , H04L43/026 , H04L43/06 , H04L43/0882
摘要： A method for managing packet traffic in a data processing network includes collecting data indicative of the amount of packet traffic traversing each of the links in the network's interconnect. The collected data includes source and destination information indicative of the source and destination of corresponding packets. A heavily used links are then identified from the collected data. Packet data associated with the heavily used link is then analyzed to identify a packet source and packet destination combination that is a significant contributor to the packet traffic on the heavily used link. In response, a process associated with the identified packet source and packet destination combination is migrated, such as to another node of the network, to reduce the traffic on the heavily used link. In one embodiment, an agent installed on each interconnect switch collects the packet data for interconnect links connected to the switch.
摘要翻译：一种用于管理数据处理网络中的分组业务的方法包括收集表示穿过网络互连中每个链路的分组流量的数据的数据。收集的数据包括指示相应分组的源和目的地的源和目的地信息。然后从收集的数据中识别出大量使用的链接。然后分析与大量使用的链路相关联的分组数据，以识别作为重度使用的链路上的分组业务的重要贡献者的分组源和分组目的地组合。作为响应，与识别的分组源和分组目的地组合相关联的进程被迁移，例如到网络的另一个节点，以减少重度使用的链路上的流量。在一个实施例中，安装在每个互连交换机上的代理收集用于连接到交换机的互连链路的分组数据。

87. 发明申请

US20070282985A1 Service Delivery Using Profile Based Management 失效
标题翻译：使用配置文件管理的服务交付
公开(公告)号：US20070282985A1
公开(公告)日：2007-12-06
申请号：US11422225
申请日：2006-06-05
申请人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
发明人： Rhonda L. Childress , Itzhack Goldberg , Lorraine M. Herger , Ziv Rafalovich , Ramakrishnan Rajamony , Eric Van Hensbergen , Martin J. Tross
IPC分类号： G06F15/173
CPC分类号： G06F9/5061 , G06F2209/5012
摘要： A computer implemented method, data processing system, and computer program product for automatically aggregating entities via a profile-driven management. A profile is created, wherein the profile includes a set of search criteria comprising one or more server attributes. A list of attributes of each server in the data processing system is obtained. Servers in the plurality of servers whose attributes meet the set of search criteria specified in the profile are then grouped to form a profile group. Once the servers are grouped into a profile, an administrative action may be performed on all of the servers in the profile group simultaneously.
摘要翻译：一种计算机实现的方法，数据处理系统和计算机程序产品，用于通过简档驱动管理自动聚合实体。创建简档，其中简档包括一组包括一个或多个服务器属性的搜索准则。获得数据处理系统中每个服务器的属性列表。然后将其属性符合在配置文件中指定的搜索条件集合的多个服务器中的服务器分组以形成配置文件组。一旦将服务器分组到配置文件中，可以同时在配置文件组中的所有服务器上执行管理操作。

88. 发明申请

US20070136535A1 System and Method for Reducing Unnecessary Cache Operations 失效
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US20070136535A1
公开(公告)日：2007-06-14
申请号：US11674960
申请日：2007-02-14
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

89. 发明申请

US20060277366A1 System and method of managing cache hierarchies with adaptive mechanisms 失效
标题翻译：用自适应机制管理缓存层次的系统和方法
公开(公告)号：US20060277366A1
公开(公告)日：2006-12-07
申请号：US11143328
申请日：2005-06-02
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/0822
摘要： A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.
摘要翻译：一种使用自适应机制管理缓存层次结构的系统和方法。本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存（源高速缓存）中选择用于逐出的数据块，检查数据结构以确定是否存在指示数据块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器，并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。此外，本发明的优选实施例包括响应于确定条目存在于数据结构中，从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块内存缓存被驱逐。

90. 发明授权

US07079341B2 Multiple disk, variable RPM data storage system for reducing power consumption 失效
标题翻译：多磁盘，可变RPM数据存储系统，用于降低功耗
公开(公告)号：US07079341B2
公开(公告)日：2006-07-18
申请号：US10798935
申请日：2004-03-11
申请人： Michael David Kistler , Ramakrishnan Rajamony
发明人： Michael David Kistler , Ramakrishnan Rajamony
IPC分类号： G11B5/09 , G06F12/00
CPC分类号： G11B19/28 , G06F11/3419 , G06F11/3433 , G06F11/3485 , G06F2201/81 , Y02D10/34
摘要： A data storage system includes a set of disks where each disk is operable in a plurality of discrete angular velocity levels. A disk controller controls the angular velocity of each active disk. The controller replicates a first portion of data on a plurality of the disks stores a second class of data in the set of disks without replication. The disk controller routes data requests to one of the active disks based, at least in part, on the current loading of the active disks to maintain balanced loading on the active disks. The disk controller alters the angular velocity of at least one of the active disks upon detecting that the latency of one or more of the data requests differs from a specified threshold. In this manner, the disk controller maintains the angular velocity of the active disks at approximately the same minimum angular velocity needed to attain acceptable performance. The disk controller may replicate the first portion of data on each of the disks in the set of disks. The disk controller may balance the loading on the active disks by routing an incoming request to the active disk with the least loading. The disk controller may maintain each of the active disks at approximately the same angular velocity by preventing the angular velocity of any active disk from differing from the angular velocity of any other active disk by more than one discrete level. The disk controller may recognize two or more levels of request priorities. In this embodiment, the disk controller routes requests of a first priority to an active disk in a first subset of active disks based, at least in part, on the current loading of the disks in the first subset and route requests of a second priority to an active disk in a second subset of active disks based, at least in part, on the current loading of the disks in the second subset.
摘要翻译：数据存储系统包括一组盘，其中每个盘可以以多个离散的角速度水平操作。磁盘控制器控制每个活动磁盘的角速度。控制器复制多个磁盘上的数据的第一部分将第二类数据存储在该组磁盘中，而不进行复制。至少部分地，磁盘控制器将数据请求路由到其中一个活动磁盘，目的是加载活动磁盘以维持活动磁盘上的平衡加载。在检测到一个或多个数据请求的等待时间与指定的阈值不同时，磁盘控制器改变至少一个活动盘的角速度。以这种方式，盘控制器将活动盘的角速度保持在达到可接受性能所需的大致相同的最小角速度。磁盘控制器可以复制该组磁盘中每个磁盘上的第一部分数据。磁盘控制器可以通过以最小的负载将传入请求路由到活动磁盘来平衡活动磁盘上的负载。磁盘控制器可以通过防止任何活动盘的角速度与任何其他活动盘的角速度不同而超过一个离散水平而将每个活动盘保持在大致相同的角速度。磁盘控制器可以识别两个或多个级别的请求优先级。在该实施例中，盘控制器至少部分地基于第一子集中的磁盘的当前加载并将第二优先级的请求路由到第一优先级的第一优先级的请求，将其发送到活动盘的第一子集中至少部分地基于第二子集中的磁盘的当前加载的活动磁盘的第二子集中的活动磁盘。

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