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81. 发明申请

US20130344677A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130344677A1
公开(公告)日：2013-12-26
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

82. 发明申请

US20130341754A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130341754A1
公开(公告)日：2013-12-26
申请号：US13531654
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

83. 发明申请

US20130270627A1 FinFET NON-VOLATILE MEMORY AND METHOD OF FABRICATION 失效
标题翻译： FinFET非易失性存储器和制造方法
公开(公告)号：US20130270627A1
公开(公告)日：2013-10-17
申请号：US13444219
申请日：2012-04-11
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/28273 , H01L21/28282 , H01L21/845 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1157 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer.
摘要翻译：一种制造FinFET非易失性存储器件和FinFET非易失性存储器件结构的方法。提供衬底并且在衬底上沉积半导体材料层。在半导体材料上沉积硬掩模，并且将该结构图案化以形成翅片。电荷存储层沉积在结构上，包括鳍片，并且其部分使用成角度的离子注入工艺被损坏。损坏的部分被去除并且栅极结构形成在翅片的任一侧，只有一侧具有电荷存储层。

84. 发明授权

US08546228B2 Strained thin body CMOS device having vertically raised source/drain stressors with single spacer 有权
标题翻译：应变的薄体CMOS器件具有单个间隔物的垂直升高的源/漏应力源
公开(公告)号：US08546228B2
公开(公告)日：2013-10-01
申请号：US12816399
申请日：2010-06-16
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一在图案化的栅极结构下方的半导体衬底的沟道区上。

85. 发明申请

US20130175595A1 INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC 有权
标题翻译：集成电路，包括DRAM和SRAM /逻辑
公开(公告)号：US20130175595A1
公开(公告)日：2013-07-11
申请号：US13344885
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1052 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/1116 , H01L27/1203 , H01L27/1207
摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
摘要翻译：集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。还公开了制造集成电路的方法。

86. 发明申请

US20130146975A1 SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT WITH HIGH-K/METAL GATE WITHOUT HIGH-K DIRECT CONTACT WITH STI 审中-公开
标题翻译：具有高K /金属栅的半导体器件和集成电路，与高K直接接触STI
公开(公告)号：US20130146975A1
公开(公告)日：2013-06-13
申请号：US13316677
申请日：2011-12-12
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823462 , H01L21/823481 , H01L29/7833
摘要： A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device.
摘要翻译：具有高k /金属栅极的方法，半导体器件和集成电路，无需与STI直接接触。将高k电介质和焊盘膜直接沉积到半导体衬底上。执行浅沟槽隔离，其中浅沟槽直接蚀刻到衬垫膜，高k材料和衬底中。浅沟槽衬有氧扩散阻挡层，随后填充有绝缘介电材料。此后，衬垫膜和绝缘电介质凹陷到氧扩散阻挡层仍然保留在绝缘电介质和高k材料之间的点，防止其间的任何接触。之后形成覆盖该器件的导电栅极。

87. 发明授权

US08455932B2 Local interconnect structure self-aligned to gate structure 有权
标题翻译：局部互连结构自对准到门结构
公开(公告)号：US08455932B2
公开(公告)日：2013-06-04
申请号：US13102073
申请日：2011-05-06
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/1104 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/7834
摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.
摘要翻译：采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

88. 发明授权

US08455308B2 Fully-depleted SON 失效
标题翻译：完全耗尽的SON
公开(公告)号：US08455308B2
公开(公告)日：2013-06-04
申请号：US13048977
申请日：2011-03-16
申请人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L29/786 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.
摘要翻译：半导体器件和半导体器件的制造方法。半导体器件包括半导体衬底，绝缘层，第一半导体层，电介质层，第二半导体层，源极和漏极结，栅极和间隔物。该方法包括以下步骤：形成半导体衬底，形成浅沟槽隔离层，生长第一外延层，生长第二外延层，形成栅极，形成间隔物，执行反应离子蚀刻，去除第一外延层，用电介质填充空隙，蚀刻电介质的一部分，生长硅层，注入源极和漏极结，以及形成延伸。

89. 发明申请

US20130082311A1 SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS 审中-公开
公开(公告)号：US20130082311A1
公开(公告)日：2013-04-04
申请号：US13609747
申请日：2012-09-11
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.

90. 发明授权

US08404540B2 Device and method of reducing junction leakage 有权
标题翻译：减少结漏电的装置和方法
公开(公告)号：US08404540B2
公开(公告)日：2013-03-26
申请号：US13446602
申请日：2012-04-13
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/8238
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译：用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。

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