专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US5438009A Method of fabrication of MOSFET device with buried bit line 失效
标题翻译：具有掩埋位线的MOSFET器件的制造方法
公开(公告)号：US5438009A
公开(公告)日：1995-08-01
申请号：US100307
申请日：1993-04-02
申请人： Ming-Tzong Yang , Gary Hong
发明人： Ming-Tzong Yang , Gary Hong
IPC分类号： H01L27/108 , H01L27/00 , H01L21/70
CPC分类号： H01L27/10808
摘要： A doped FET DRAM includes a silicon substrate, with a buried bit line in the silicon substrate. A plug extends down through the substrate to the bit line. A source region and a drain region are positioned above the plug in the substrate with one thereof connected to the plug with a layer of gate oxide above the source region and drain region. A gate above the gate oxide is juxtaposed with the source region and drain region. The source is connected to a capacitor formed of two layers of polysilicon separated by a dielectric of an ONO oxide layer.
摘要翻译：掺杂FET DRAM包括在硅衬底中具有掩埋位线的硅衬底。插头通过衬底向下延伸到位线。源极区域和漏极区域位于衬底上的插塞上方，其中一个源极与源极区域和漏极区域上方连接有栅极氧化物层。栅极氧化物上方的栅极与源区和漏区并列。源极连接到由由ONO氧化物层的电介质隔开的两层多晶硅形成的电容器。

82. 发明授权

US5429976A Self-aligned method for forming polysilicon word lines on top of gate electrodes to increase capacitance of a stacked capacitor in a DRAM cell 失效
标题翻译：用于在栅电极顶部形成多晶硅字线的自对准方法，以增加DRAM单元中层叠电容器的电容
公开(公告)号：US5429976A
公开(公告)日：1995-07-04
申请号：US158787
申请日：1993-12-01
申请人： Gary Hong , Cheng-Han Huang
发明人： Gary Hong , Cheng-Han Huang
IPC分类号： H01L21/02 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L28/40 , H01L27/10808
摘要： A method is described for forming a dynamic random access memory cell capacitor in which polysilicon word lines are formed in a self-aligned method on top of the gate electrodes of the memory cell wherein the polysilicon word lines act to increase the surface area and hence to increase the capacitance of the capacitor.
摘要翻译：描述了一种用于形成动态随机存取存储单元电容器的方法，其中多晶硅字线以自对准方法形成在存储单元的栅电极之上，其中多晶硅字线用于增加表面积，因此，增加电容的电容。

83. 发明授权

US5395779A Process of manufacture of split gate EPROM device 失效
标题翻译：分闸门EPROM器件制造工艺
公开(公告)号：US5395779A
公开(公告)日：1995-03-07
申请号：US224695
申请日：1994-04-08
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/336 , H01L27/115 , H01L29/423 , H01L21/265
CPC分类号： H01L29/66825 , H01L29/4232 , H01L27/115
摘要： Fabrication of a MOSFET comprises, forming a dielectric layer on a substrate and a sacrificial structure on portions of the dielectric layer, forming a first polysilicon layer over the sacrificial structure and other exposed surfaces of the device, patterning the first polysilicon layer and the dielectric layer by masking and etching to form a stepped electrode structure partially upon the sacrificial structure and partially upon the other exposed surfaces of the device, applying ion implantation into the substrate outside of the area covered by the stepped electrode structure, removing the sacrificial layer from the surface of the substrate and from beneath the stepped electrode structure leaving an overhanging surface of the stepped electrode structure, forming a second layer of dielectric material on the exposed surfaces of the stepped electrode structure and the substrate, and forming a second polysilicon layer over and under overhanging portions the second layer of dielectric material and the substrate.
摘要翻译： MOSFET的制造包括：在基底上形成电介质层和在电介质层的部分上形成牺牲结构，在牺牲结构和器件的其它暴露表面上形成第一多晶硅层，图案化第一多晶硅层和电介质层通过掩模和蚀刻以部分地在牺牲结构上形成阶梯状电极结构，并部分地在器件的其他暴露表面上形成阶梯状电极结构，将离子注入施加到由阶梯状电极结构覆盖的区域外部的衬底中，从表面去除牺牲层并且从阶梯状电极结构的下方离开阶梯状电极结构的悬垂表面，在阶梯状电极结构和衬底的暴露表面上形成第二层电介质材料，并且在悬垂状态下形成第二多晶硅层部分第二层电介质配合物 rial和底物。

84. 发明授权

US5384478A Mask ROM process 失效
标题翻译： Mask ROM进程
公开(公告)号：US5384478A
公开(公告)日：1995-01-24
申请号：US194737
申请日：1994-02-14
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8246 , H01L27/112 , H01L29/68
CPC分类号： H01L27/1126 , H01L27/112
摘要： A semiconductor device and a method of manufacturing a semiconductor device includes the steps of forming a first conductivity type layer on one surface of a work piece comprising a semiconductor substrate. A gate oxide is formed on the surface of the substrate. A first conductive structure is formed on the gate oxide consisting essentially of polysilicon. An insulating structure is formed in contact with the first conductive structure. Material is removed from the surface of the first conductive structure to expose at least a portion of the surface of the first layer, and to form on the remaining structure on the workpiece a second conductive structure consisting essentially of polysilicon. The polysilicon is in electrical contact with the first conductive structure. Thus, a compound conductive structure is provided on the work piece.
摘要翻译：半导体器件和半导体器件的制造方法包括以下步骤：在包括半导体衬底的工件的一个表面上形成第一导电类型层。栅极氧化物形成在衬底的表面上。在基本上由多晶硅组成的栅极氧化物上形成第一导电结构。绝缘结构形成为与第一导电结构接触。从第一导电结构的表面去除材料以暴露第一层的表面的至少一部分，并且在工件上的剩余结构上形成基本上由多晶硅组成的第二导电结构。多晶硅与第一导电结构电接触。因此，在工件上设置复合导电结构。

85. 发明授权

US5383149A Ulsi mask ROM structure and method of manufacture 失效
标题翻译： Ulsi面具ROM结构及制造方法
公开(公告)号：US5383149A
公开(公告)日：1995-01-17
申请号：US294855
申请日：1994-08-29
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8246 , H01L27/112 , G11C17/12
CPC分类号： H01L27/112
摘要： A ROM device provides a double density memory array. The word line array is composed of transversely disposed conductors sandwiched between two arrays of bit lines which are orthogonally disposed relative to the word line array. The two arrays of bit lines are stacked with one above and with one below the word line array. A first gate oxide layer is located between the word line array and a first one of the array of bit lines and a second gate oxide layer is located between the word line array and a the other of the arrays of bit lines. The two parallel sets of polysilicon thin, film transistors are formed with the word lines serving as gates for the transistors.
摘要翻译： ROM设备提供双密度存储器阵列。字线阵列由夹在相对于字线阵列正交设置的位线阵列之间的横向布置的导体组成。位线的两个阵列以一个上面堆叠，并且一个在字线阵列下方堆叠。第一栅极氧化物层位于字线阵列和位线阵列中的第一栅极氧化物层之间，并且第二栅极氧化物层位于字线阵列和位线阵列中的另一个之间。形成两个并联的多晶硅薄膜晶体管，其中字线用作晶体管的栅极。

86. 发明授权

US5308777A Mask ROM process 失效
标题翻译： Mask ROM进程
公开(公告)号：US5308777A
公开(公告)日：1994-05-03
申请号：US98044
申请日：1993-07-28
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/265
CPC分类号： H01L27/1126 , H01L27/112
摘要： A semiconductor device and a method of manufacturing a semiconductor device includes the steps of forming a first conductivity type layer on one surface of a work piece comprising a semiconductor substrate. A gate oxide is formed on the surface of the substrate. A first conductive structure is formed on the gate oxide consisting essentially of polysilicon. An insulating structure is formed in contact with the first conductive structure. Material is removed from the surface of the first conductive structure to expose at least a portion of the surface of the first layer, and to form on the remaining structure on the workpiece a second conductive structure consisting essentially of polysilicon. The polysilicon is in electrical contact with the first conductive structure. Thus, a compound conductive structure is provided on the work piece.
摘要翻译：半导体器件和半导体器件的制造方法包括以下步骤：在包括半导体衬底的工件的一个表面上形成第一导电类型层。栅极氧化物形成在衬底的表面上。在基本上由多晶硅组成的栅极氧化物上形成第一导电结构。绝缘结构形成为与第一导电结构接触。从第一导电结构的表面去除材料以暴露第一层的表面的至少一部分，并且在工件上的剩余结构上形成基本上由多晶硅组成的第二导电结构。多晶硅与第一导电结构电接触。因此，在工件上设置复合导电结构。

87. 发明授权

US06396745B1 Vertical two-transistor flash memory 有权
标题翻译：垂直双晶体管闪存
公开(公告)号：US06396745B1
公开(公告)日：2002-05-28
申请号：US09783868
申请日：2001-02-15
申请人： Gary Hong , Hwi-Huang Chen , Wen-Chi Ting
发明人： Gary Hong , Hwi-Huang Chen , Wen-Chi Ting
IPC分类号： G11C700
CPC分类号： G11C16/3427 , G11C16/0433 , H01L29/42324 , H01L29/7883
摘要： In present invention we provide a vertical two-transistor memory cell consisted of a MOS transistor and an ETOX cell. One of the drain or source of the MOS transistor is connected to the control gate of the ETOX cell, the other is acted as the control gate of the vertical two-transistor memory cell and is connected to a control line. And the gate of the MOS transistor is acted as the select gate of the vertical two-transistor memory cell and is connected to a word line. The drain of ETOX cell is connected to a bit line, and the source of ETOX cell is grounded. The vertical two-transistor memory cell can be programmed by channel Fowler-Nordheim tunneling of electrons which is injected from the substrate through the channel and tunnel oxide into the floating gate. Such memory cell can avoid the word line disturb by controlling the word line. The memory cell can be also erased by channel Fowler-Nordheim tunneling, in which the electrons is withdrawn from the floating gate through the tunnel oxide and channel to the substrate. In addition, the vertical two-transistor memory cell can be also programmed by conventional methods such as hot electron injection and drain Fowler-Nordheim tunneling, and can be also erased by negative gate source erase or drain Fowler-Nordheim tunneling erase.
摘要翻译：在本发明中，我们提供了由MOS晶体管和ETOX单元组成的垂直双晶体管存储单元。 MOS晶体管的漏极或源极之一连接到ETOX单元的控制栅极，另一个作为垂直双晶体管存储单元的控制栅极并连接到控制线。并且MOS晶体管的栅极用作垂直双晶体管存储单元的选择栅极并连接到字线。 ETOX电池的漏极连接到位线，ETOX电池的源极接地。垂直双晶体管存储单元可以通过通道Fowler-Nordheim隧道进行编程，电子从基板通过沟道注入并将隧道氧化物注入浮栅。这样的存储单元可以通过控制字线来避免字线干扰。还可以通过通道Fowler-Nordheim隧道擦除存储单元，其中电子通过隧道氧化物和通道从浮栅取出到衬底。此外，垂直双晶体管存储单元也可以通过诸如热电子注入和漏极Fowler-Nordheim隧道的常规方法进行编程，并且还可以通过负栅极源擦除或漏极Fowler-Nordheim隧道擦除来擦除。

88. 发明授权

US06235576B1 Method for manufacturing a cylindrical capacitor 失效
标题翻译：圆柱形电容器的制造方法
公开(公告)号：US06235576B1
公开(公告)日：2001-05-22
申请号：US09241522
申请日：1999-02-01
申请人： Gary Hong , Anchor Chen
发明人： Gary Hong , Anchor Chen
IPC分类号： H01L2120
CPC分类号： H01L28/92 , H01L21/76895 , H01L27/10852
摘要： A method for manufacturing a cylindrical capacitor on a substrate includes the steps of providing a semiconductor substrate having a first conductive layer thereon, and then forming an insulation layer over the first conductive layer. The insulation layer can be a silicon nitride layer. The insulation layer is patterned to leave a portion of the patterned insulation layer above the node contact region. Thereafter, spacers are formed on the sidewalls of the patterned insulation layer such that the spacers are formed from a material that differs from the insulation layer and the first conductive layer. Next, an etching operation is conducted using the patterned insulation layer and the spacers as a mask to remove a portion of the first conductive layer. After that, the patterned insulation layer is removed. Then, a second etching operation is carried out using the spacers as a mask so that some more material from the upper portion of the first conductive layer is removed. Ultimately, a cylindrical shape structure that serves as the lower electrode of a capacitor is formed. Finally, the spacers are removed, and then a dielectric layer and a second conductive layer are sequentially formed over the cylindrical lower electrode to complete the fabrication of a cylindrical capacitor.
摘要翻译：一种用于在基板上制造圆柱形电容器的方法包括以下步骤：在其上提供具有第一导电层的半导体衬底，然后在第一导电层上形成绝缘层。绝缘层可以是氮化硅层。将绝缘层图案化以将图案化绝缘层的一部分留在节点接触区域上方。此后，在图案化绝缘层的侧壁上形成间隔物，使得间隔物由与绝缘层和第一导电层不同的材料形成。接下来，使用图案化绝缘层和间隔物作为掩模进行蚀刻操作以去除第一导电层的一部分。之后，去除图案化绝缘层。然后，使用间隔物作为掩模进行第二蚀刻操作，从而去除来自第一导电层的上部的一些更多的材料。最终，形成用作电容器的下电极的圆柱形结构。最后，去除间隔物，然后在圆柱形下电极上依次形成电介质层和第二导电层，以完成圆柱形电容器的制造。

89. 发明授权

US06232214B1 Method for fabricating inter-metal dielectric layer 有权
标题翻译：制造金属间介电层的方法
公开(公告)号：US06232214B1
公开(公告)日：2001-05-15
申请号：US09316475
申请日：1999-05-21
申请人： Claymens Lee , Gary Hong
发明人： Claymens Lee , Gary Hong
IPC分类号： H01L214763
CPC分类号： H01L21/7682
摘要： A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.
摘要翻译：一种制造金属间介电层的方法。在基板上形成几根导线，开口位于相邻的导线之间。第一电介质层填充开口，并且第一电介质层的表面低于导线的表面。在每个导线的侧壁上形成间隔物。去除第一介电层以露出间隔物的底部。形成第二电介质层以覆盖导线。

90. 发明授权

US06215147B1 Flash memory structure 有权
标题翻译：闪存结构
公开(公告)号：US06215147B1
公开(公告)日：2001-04-10
申请号：US09235261
申请日：1999-01-22
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory structure and a method of fabricating the same are provided. The flash memory structure is formed with buried bit lines that are lower in resistance, are shallower in buried depth into the substrate, and have a larger punchthrough margin than the prior art. The flash memory structure is constructed on a semiconductor substrate. A tunneling oxide layer is formed over the substrate. A plurality of floating gates is formed at predefined locations over the tunneling oxide layer. A plurality of sidewall spacers is formed on the sidewalls of the floating gates. A plurality of selective polysilicon blocks is formed over the substrate, each being formed between one neighboring pair of the floating gates. An ion-implantation process is performed to dope an impurity element through these selective polysilicon blocks into the substrate to thereby form a plurality of impurity-doped regions in the substrate to serve as a plurality of buried bit line for the flash memory device. A plurality of insulating layers is formed respectively over the selective polysilicon blocks. A dielectric layer is formed to cover all of the floating gates and the insulating layers, and finally, a plurality of control gates are formed over the dielectric layer, each being located above one of the floating gates.
摘要翻译：提供闪存结构及其制造方法。闪速存储器结构形成有电阻较低的掩埋位线，埋入深度较浅的衬底中，并且具有比现有技术更大的穿通余量。闪存结构构造在半导体衬底上。在衬底上形成隧道氧化物层。在隧道氧化物层上的预定位置处形成多个浮动栅极。多个侧壁间隔件形成在浮动栅极的侧壁上。在衬底上形成多个选择性多晶硅块，每个选择性多晶硅块形成在一对相邻的浮置栅极之间。执行离子注入工艺以将杂质元素通过这些选择性多晶硅块掺杂到衬底中，从而在衬底中形成多个杂质掺杂区域，以用作闪存器件的多个掩埋位线。分别在选择性多晶硅块上形成多个绝缘层。形成介电层以覆盖所有浮动栅极和绝缘层，最后，在电介质层上形成多个控制栅极，每个控制栅极位于浮动栅极之一上方。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式