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81. 发明授权

US06569738B2 Process for manufacturing trench gated MOSFET having drain/drift region 有权
标题翻译：制造具有漏极/漂移区域的沟槽栅控MOSFET的工艺
公开(公告)号：US06569738B2
公开(公告)日：2003-05-27
申请号：US09898652
申请日：2001-07-03
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L21/2253 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7811
摘要： A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N-type dopant is implanted through the bottom of the trench into the P-epitaxial layer to form a buried layer below the trench, and after a up-diffusion step a N drain-drift region extends between the N+ substrate and the bottom of the trench. The result is a more controllable doping profile of the N-type dopant below the trench. The body region may also be formed by implanting P-type dopant into the epitaxial layer, in which case the background doping of the epitaxial layer may be either lightly doped P- or N-type. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.
摘要翻译：在包括覆盖在N +衬底上的P型外延层的结构中形成沟槽MOSFET。通过沟槽的底部将N型掺杂剂注入到P外延层中以在沟槽下方形成掩埋层，并且在上扩散步骤之后，N漏极漂移区在N +衬底和底层之间延伸沟渠。结果是沟槽下方的N型掺杂剂的更可控的掺杂分布。体区也可以通过将P型掺杂剂注入到外延层中而形成，在这种情况下，外延层的背景掺杂可以是轻掺杂的P型或N型。根据本发明构造的MOSFET可以具有降低的阈值电压和导通电阻以及增加的穿通击穿电压。

82. 发明授权

US06475848B1 Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor 有权
标题翻译：多晶硅边缘，低功耗，高频双极晶体管和形成晶体管的方法
公开(公告)号：US06475848B1
公开(公告)日：2002-11-05
申请号：US09882600
申请日：2001-06-15
申请人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
发明人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
IPC分类号： H01L218238
CPC分类号： H01L29/66287 , H01L29/732
摘要： A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.
摘要翻译：低功率高频双极晶体管形成为具有减小基极到集电极电容的小的自对准基极区域，以及减小基极 - 发射极电容的小的自对准基极和发射极触点，以及基座阻力。基极和发射极触点形成为具有亚光刻特征尺寸。

83. 发明授权

US06380017B1 Polysilicon-edge, base-emitter super self-aligned, low-power, high-frequency bipolar transistor and method of forming the transistor 有权
标题翻译：多晶硅边缘，基极 - 发射极超自对准，低功耗，高频双极晶体管和形成晶体管的方法
公开(公告)号：US06380017B1
公开(公告)日：2002-04-30
申请号：US09882859
申请日：2001-06-15
申请人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
发明人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
IPC分类号： H01L218238
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/41708 , H01L29/732
摘要： A low-power high-frequency bipolar transistor is formed to have a small self-aligned intrinsic base region, and small self-aligned extrinsic base and emitter regions that contact the intrinsic base region. The small regions reduce the base resistance, the base-to-collector capacitance, and the base-to-emitter capacitance.
摘要翻译：低功率高频双极晶体管被形成为具有小的自对准本征基极区域，以及接触本征基极区域的小的自对准的非本征基极和发射极区域。小区域降低了基极电阻，基极 - 集电极电容和基极 - 发射极电容。

84. 发明授权

US6140678A Trench-gated power MOSFET with protective diode 失效
标题翻译：带保护二极管的沟槽式功率MOSFET
公开(公告)号：US6140678A
公开(公告)日：2000-10-31
申请号：US962867
申请日：1997-11-03
申请人： Wayne B. Grabowski , Richard K. Williams , Mohamed N. Darwish
发明人： Wayne B. Grabowski , Richard K. Williams , Mohamed N. Darwish
IPC分类号： H01L21/336 , H01L27/02 , H01L29/06 , H01L29/10 , H01L29/78 , H01L29/745
CPC分类号： H01L27/0255 , H01L29/1095 , H01L29/7808 , H01L29/7813 , H01L29/7827 , H01L29/0696
摘要： A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a diode that is connected in parallel with the channel region in each of the MOSFET cells. The protective diffusion, which replaces the deep central diffusion taught in U.S. Pat. No. 5,072,266, prevents impact ionization and the resulting generation of carriers near the corners of the gate trench, which can damage or rupture the gate oxide layer. Moreover, the diode can be designed to have a breakdown voltage which limits the strength of the electric field across the gate oxide layer. The elimination of a deep central diffusion permits an increase in cell density and improves the on-resistance of the MOSFET. Specifications for a number of commercially acceptable devices are given.
摘要翻译：功率MOSFET包括限定多个MOSFET单元的沟槽栅极。产生保护性扩散，优选在非活性电池中，以形成与每个MOSFET单元中的沟道区并联连接的二极管。保护性扩散取代了美国专利中教导的深部中心扩散。 5,072,266号文件防止了栅极沟槽角落附近的碰撞电离和载流子的产生，这可能损坏或破坏栅极氧化物层。此外，二极管可以设计成具有限制栅极氧化物层两端的电场强度的击穿电压。消除深的中心扩散允许增加电池密度并改善MOSFET的导通电阻。给出了许多商业上可接受的装置的规格。

85. 发明授权

US10062788B2 Semiconductor on insulator devices containing permanent charge 有权
公开(公告)号：US10062788B2
公开(公告)日：2018-08-28
申请号：US12431005
申请日：2009-04-28
申请人： Amit Paul , Mohamed N. Darwish
发明人： Amit Paul , Mohamed N. Darwish
IPC分类号： H01L29/78 , H01L29/786 , H01L29/06 , H01L29/40 , H01L29/08 , H01L29/423
CPC分类号： H01L29/78624 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0873 , H01L29/0878 , H01L29/0886 , H01L29/408 , H01L29/42368 , H01L29/7824 , H01L29/7825
摘要： A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too.

86. 发明授权

US08659074B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08659074B2
公开(公告)日：2014-02-25
申请号：US11971123
申请日：2008-01-08
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.
摘要翻译：半导体器件包括形成在其上的第一导电类型的半导体层和第二导电类型的半导体层。半导体器件还包括延伸第二预定距离的第二预定距离的第二预定距离的第二导电类型的半导体层的主体层和延伸到第二导电类型的半导体层的一对沟槽。一对沟槽中的每一个基本上由设置在其中的介电材料组成，并且存在于第二导电类型的半导体层中的掺杂杂质的浓度和该对沟槽之间的距离限定了半导体器件的电特性。半导体器件还包括耦合到第二导电类型的半导体层的控制栅极和耦合到第二导电类型的半导体层的源极区域。

87. 发明授权

US08592906B2 High-voltage semiconductor device with lateral series capacitive structure 有权
标题翻译：具有横向串联电容结构的高压半导体器件
公开(公告)号：US08592906B2
公开(公告)日：2013-11-26
申请号：US13325712
申请日：2011-12-14
申请人： Mohamed N. Darwish , Robert Kuo-Chang Yang
发明人： Mohamed N. Darwish , Robert Kuo-Chang Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/407 , H01L29/66659
摘要： A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region.
摘要翻译：半导体器件包括半导体衬底，沿着半导体衬底的顶表面延伸的源极区域，沿着半导体衬底的顶表面延伸的漏极区域和设置在源极区域和半导体衬底之间的半导体衬底内的场整形区域漏区。通过场整形区域从源极区域延伸到漏极区域的半导体衬底的横截面包括绝缘区域。半导体器件还包括在源极区域和漏极区域之间设置在半导体衬底内的有源区域。有源区域在垂直于通过场整形区域从源极区域延伸到漏极区域的半导体衬底的横截面的方向上与场整形区域相邻设置。

88. 发明授权

US08420483B2 Method of manufacture for a semiconductor device 有权
公开(公告)号：US08420483B2
公开(公告)日：2013-04-16
申请号：US11971169
申请日：2008-01-08
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.

89. 发明授权

US08058682B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08058682B2
公开(公告)日：2011-11-15
申请号：US11971096
申请日：2008-01-08
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor structure includes a number of semiconductor regions, a pair of dielectric regions and a pair of terminals. The first and second regions of the structure are respectively coupled to the first and second terminals. The third region of the structure is disposed between the first and second regions. The dielectric regions extend into the third region. A concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the structure. The electrical characteristic of the structure is independent of the width of the dielectric regions width. The first and second regions are of opposite conductivity types. The structure optionally includes a fourth region that extends into the third region, and surrounds a portion of the pair of dielectric regions. The interface region between the dielectric regions and the fourth region includes intentionally introduced charges.
摘要翻译：半导体结构包括多个半导体区域，一对电介质区域和一对端子。该结构的第一和第二区域分别耦合到第一和第二端子。结构的第三区域设置在第一和第二区域之间。电介质区域延伸到第三区域。存在于第三区域中的掺杂杂质的浓度和电介质区域之间的距离限定了该结构的电特性。该结构的电气特性与电介质区域的宽度无关。第一和第二区域具有相反的导电类型。该结构可选地包括延伸到第三区域中并围绕该对电介质区域的一部分的第四区域。电介质区域和第四区域之间的界面区域包括有意引入的电荷。

90. 发明授权

US07964913B2 Power MOS transistor incorporating fixed charges that balance the charge in the drift region 有权
标题翻译：掺入固定电荷的功率MOS晶体管，以平衡漂移区域中的电荷
公开(公告)号：US07964913B2
公开(公告)日：2011-06-21
申请号：US11971139
申请日：2008-01-08
申请人： Mohamed N. Darwish
发明人： Mohamed N. Darwish
IPC分类号： H01L29/423
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/0217 , H01L21/02321 , H01L21/2003 , H01L21/265 , H01L21/2658 , H01L21/26586 , H01L21/28008 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/823885 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4236 , H01L29/42368 , H01L29/66537 , H01L29/66666 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.
摘要翻译：半导体器件包括形成在其上的第一导电类型的半导体层和第二导电类型的半导体层。第二导电类型的半导体层的特征在于第一厚度。半导体器件包括具有预定深度并延伸到第二导电类型的半导体层的一组沟槽，从而限定设置在第二导电类型的半导体层与每个沟槽之间的界面区域。沟槽包括基本上由布置在其中的介电材料组成的远端部分和包括电介质材料的近端部分和设置在沟槽的近端部分中的电介质材料内部的栅极材料。半导体器件还包括耦合到第二导电类型的半导体层的源极区域。

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