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    • 82. 发明授权
    • Electronically programmable antifuse and circuits made therewith
    • 电子可编程反熔丝和由其制成的电路
    • US06879021B1
    • 2005-04-12
    • US10605523
    • 2003-10-06
    • John A. FitfieldWagdi W. AbadeerWilliam R. Tonti
    • John A. FitfieldWagdi W. AbadeerWilliam R. Tonti
    • H01L23/525H01L27/12
    • H01L23/5252H01L2924/0002H01L2924/3011H01L2924/00
    • An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
    • 一种反熔丝装置(120),其包括彼此串联布置的偏置元件(124)和可编程反熔丝元件(128),以形成具有位于偏置和反熔丝元件之间的输出节点(F)的分压器。 当反熔丝装置处于其未编程状态时,偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时,偏置元件保持不导电,但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时,在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路(228)容易地感测。
    • 86. 发明授权
    • Tungsten hot wire current limiter for ESD protection
    • 钨热线电流限制器,用于ESD保护
    • US06700164B1
    • 2004-03-02
    • US09611812
    • 2000-07-07
    • Ciaran J. BrennanKevin A. DuncanWilliam R. TontiSteven H. Voldman
    • Ciaran J. BrennanKevin A. DuncanWilliam R. TontiSteven H. Voldman
    • H01L2362
    • H01L23/62H01L2924/0002H01L2924/3011H01L2924/00
    • In order to divert damaging currents into an electrostatic discharge (ESD) protection device during an ESD event, a tungsten wire resistor is incorporated into a current path connected in parallel with the ESD protection circuitry. The tungsten wire resistor has linear current-voltage (IV) characteristics at low currents, and non-linear IV characteristics at high current levels. The width and length of the resistor is chosen so that the resistor experiences significant self-heating caused by the higher currents generated by the ESD event. At a higher current level, the resistor becomes hot and its resistance increases dramatically. As a result the voltage drop across it increases thus diverting excess current into the parallel connected ESD protection circuitry. This limits the current through the resistor and thereby protects circuit elements in series with the resistor.
    • 为了在ESD事件期间将损坏电流转移到静电放电(ESD)保护装置中,钨线电阻器被并入到与ESD保护电路并联连接的电流路径中。 钨丝电阻器在低电流下具有线性电流电压(IV)特性,在高电流水平下具有非线性IV特性。 选择电阻器的宽度和长度,使得电阻器经受由ESD事件产生的较高电流引起的显着的自身加热。 在较高的电流水平,电阻变热,其电阻急剧增加。 因此,其上的压降增加,从而将过剩电流转移到并联的ESD保护电路中。 这限制了通过电阻器的电流,从而保护与电阻器串联的电路元件。
    • 87. 发明授权
    • Implant sequence for multi-function semiconductor structure and method
    • 多功能半导体结构和方法的种植体序列
    • US06440788B2
    • 2002-08-27
    • US09895159
    • 2001-07-02
    • Jack A. MandelmanEdward J. NowakWilliam R. Tonti
    • Jack A. MandelmanEdward J. NowakWilliam R. Tonti
    • H01L2710
    • H01L29/7302H01L21/84H01L27/1203
    • A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.
    • 提供了多功能半导体器件。 该器件包括并联形成的双极晶体管和FET。 半导体衬底设置在绝缘层上。 源极/发射极区域和漏极区域形成在半导体衬底中并且与其间的体区域的第一相对侧边界。 在源极/发射极区域和漏极区域之间的衬底上方形成栅极,以形成具有包括栅极,源极/发射极区域和漏极区域的三个端子的FET。 集电极区域形成在与衬底邻接的衬底中,并在栅极和漏极区域之下进一步延伸。 形成具有三个端子的双极晶体管,其包括基极区域,源极/发射极和集电极区域。 集电极区域和源极/发射极区域之间的最短距离定义基极宽度。
    • 89. 发明授权
    • Shared body and diffusion contact structure and method for fabricating same
    • 共享体和扩散接触结构及其制造方法
    • US06429477B1
    • 2002-08-06
    • US09702315
    • 2000-10-31
    • Jack A. MandelmanRama DivakaruniWilliam R. Tonti
    • Jack A. MandelmanRama DivakaruniWilliam R. Tonti
    • H01L2976
    • H01L27/10861H01L21/743H01L21/76897H01L27/0214H01L27/10888H01L27/1203
    • The preferred embodiment overcomes the difficulties found in the background art by providing a body contact and diffusion contact formed in a single shared via for silicon on insulator (SOI) technologies. By forming the body contact and diffusion contact in a single shared via, device size is minimized and performance is improved. Particularly, the formed body contact connects the SOI layer with the underlying substrate to avoid instabilities and leakage resulting from a floating SOI channel region. The formed diffusion contact connects device diffusions to above wiring to facilitate device operation. By providing the body contact and diffusion contact together in a single shared via, the preferred embodiment avoids the area penalty that would result from separate contacts. Additionally, the preferred embodiment provides a body contact that is self aligned with other devices, minimizing tolerances needed while minimizing process complexity. Additionally, the shared via body contact and diffusion contact can be selectively formed borderless to adjacent gate conductors in the device.
    • 优选实施例通过提供在用于绝缘体上硅(SOI)技术的单个共享通孔中形成的体接触和扩散接触来克服背景技术中发现的困难。 通过在单个共享通孔中形成体接触和扩散接触,器件尺寸最小化并且性能得到改善。 特别地,形成的体接触将SOI层与底层衬底连接,以避免由浮动SOI沟道区产生的不稳定性和漏电。 形成的扩散触点将器件扩散连接到上述布线以便于器件操作。 通过在单个共享通孔中将身体接触和扩散接触提供在一起,优选的实施例避免了由单独接触引起的区域损失。 此外,优选实施例提供与其他装置自对准的身体接触,使尽可能少的过程复杂性所需的公差最小化。 此外,共享的通孔体接触和扩散接触可以选择性地形成与设备中的相邻栅极导体无边界。