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81. 发明授权

US06240474B1 Pipelined read transfers 失效
标题翻译：流水线读取传输
公开(公告)号：US06240474B1
公开(公告)日：2001-05-29
申请号：US08931705
申请日：1997-09-16
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/28 , G06F13/4027
摘要： A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request.
摘要翻译：提供了一种实现流水线读取传输或PRT的方法和实现系统。 PRT包括请求阶段和响应阶段。 PRT请求阶段涉及PRT请求主机传送到PRT请求目标，源地址，目的地地址和正在请求的数据的传输大小。在PRT响应阶段，PRT请求目标成为PRT响应主机，即PCI总线主机，并启动完成在发起PRT请求中请求的事务。

82. 发明授权

US06175888B1 Dual host bridge with peer to peer support 失效
标题翻译：双主机桥与对等支持
公开(公告)号：US06175888B1
公开(公告)日：2001-01-16
申请号：US08627810
申请日：1996-04-10
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/36 , G06F13/4027
摘要： A data processing system includes a processor, system memory and a number of peripheral devices, and one or more bridges which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus. The host bridge provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces in provided.
摘要翻译：数据处理系统包括处理器，系统存储器和多个外围设备以及可以在处理器，存储器和外围设备以及诸如网络中的其它主机或外围设备之间连接的一个或多个桥接器。诸如PCI主机桥的桥连接在主总线（例如系统总线）和辅助总线之间。主桥提供双主机桥功能，其创建两个辅助总线接口。这允许在一个双主机桥下增加负载能力，而在一个正常主桥下允许的较少数量的时隙。还包括附加的控制逻辑，用于提供仲裁控制和用于转向事务到适当的总线接口。另外，提供的两个辅助总线接口的对等支持。

83. 发明授权

US5887144A Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches 失效
标题翻译：通过使用在线开关增加总线的负载和扩展能力的方法和系统
公开(公告)号：US5887144A
公开(公告)日：1999-03-23
申请号：US753116
申请日：1996-11-20
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4068
摘要： A method and system for expanding the load capabilities of a bus, such as the PCI bus. The system includes a primary bus, a plurality of secondary buses for connecting additional devices, a plurality of in-line switches, an arbiter, and control logic means. The plurality of in-line switches are used for connecting the primary bus to a corresponding one of the secondary buses, each one of the switches having an enable line for receiving a signal to enable or disable the switch. The arbiter is used for receiving requests for control of the primary bus, and for selecting one of the requests as a master for the control. The control logic means is used for enabling and disabling each of the switches, via the corresponding enable line, for connection or disconnection to the primary bus. The control logic means includes means, coupled to the arbiter, for gaining control over the primary bus prior to granting control to the master, and means for transmitting, during control over the primary bus, an enable signal to the switches corresponding to the secondary buses desired to be connected to the primary bus.
摘要翻译：一种用于扩展总线（如PCI总线）的负载能力的方法和系统。该系统包括主总线，用于连接附加设备的多个次总线，多个在线交换机，仲裁器和控制逻辑装置。多个在线开关用于将主总线连接到相应的一个辅助总线，每个开关具有用于接收信号以启用或禁用开关的使能线。仲裁器用于接收对主总线的控制请求，并用于选择其中一个请求作为控制主机。控制逻辑装置用于通过相应的使能线路使能和禁用每个开关用于连接或断开到主总线。控制逻辑装置包括耦合到仲裁器的装置，用于在向主机授予控制之前获得对主总线的控制，以及用于在对主总线进行控制期间向对应于辅助总线的开关发送使能信号的装置希望连接到主总线。

84. 发明授权

US5784576A Method and apparatus for adding and removing components of a data processing system without powering down 失效
标题翻译：用于在不掉电的情况下添加和移除数据处理系统的组件的方法和装置
公开(公告)号：US5784576A
公开(公告)日：1998-07-21
申请号：US741466
申请日：1996-10-31
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Richard Allen Kelley
IPC分类号： G06F13/40 , G06F13/00 , H03K17/693 , H04B1/44
CPC分类号： G06F13/4081
摘要： A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).
摘要翻译：一种方法和系统，用于提供在不向系统供电的情况下添加或删除数据处理系统的组件的能力（“热插拔”）。该系统包括驻留在主机桥中的仲裁器，控制和电源逻辑以及耦合到总线的多个在线开关模块。每个在线开关模块为连接到其上的负载提供隔离。主机桥与控制和电源逻辑结合实施热插拔操作，例如将功率上升和下降到选定的插槽，并激活适当的在线开关以进行从负载（目标/控制）的通信主）。

85. 发明授权

US08281075B2 Processor system and methods of triggering a block move using a system bus write command initiated by user code 失效
标题翻译：使用由用户代码启动的系统总线写入命令来触发块移动的处理器系统和方法
公开(公告)号：US08281075B2
公开(公告)日：2012-10-02
申请号：US12423355
申请日：2009-04-14
申请人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F13/00 , G06F13/36 , G06F13/38 , G06F9/315
CPC分类号： G06F12/1458 , G06F9/30047 , G06F9/30087 , G06F12/0893
摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.
摘要翻译：用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核中的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中）记忆）。从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令的从设备处理特定请求类型命令。可信内核可能包含在管理程序或操作系统中。

86. 发明授权

US07849298B2 Enhanced processor virtualization mechanism via saving and restoring soft processor/system states 失效
标题翻译：通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制
公开(公告)号：US07849298B2
公开(公告)日：2010-12-07
申请号：US12352462
申请日：2009-01-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30123 , G06F9/30116 , G06F9/3013 , G06F9/462
摘要： A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.
摘要翻译：公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软状态信息。软状态经由存储器接口传送到与处理器相关联的存储器。优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。此后，当再次执行处理时，可以从存储器恢复存储的软状态。

87. 发明申请

US20100268890A1 INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW 有权
标题翻译：信息处理系统，具有立即调度在双存储单元缓存中的负载运算，具有单个分配到写/读数据流
公开(公告)号：US20100268890A1
公开(公告)日：2010-10-21
申请号：US12424228
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0897
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。

88. 发明申请

US20100268883A1 Information Handling System with Immediate Scheduling of Load Operations and Fine-Grained Access to Cache Memory 有权
标题翻译：信息处理系统，即时调度负载操作和细粒度访问高速缓存
公开(公告)号：US20100268883A1
公开(公告)日：2010-10-21
申请号：US12424332
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。控制逻辑确定每个加载操作或存储操作的大小要求。当高速缓冲存储器系统执行存储操作或加载操作时，存储器系统访问它需要执行操作的高速缓存行的部分，而不是访问整个高速缓存行。

89. 发明授权

US07689777B2 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US07689777B2
公开(公告)日：2010-03-30
申请号：US11951770
申请日：2007-12-06
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下，否定受保护成员的选择。

90. 发明申请

US20090198867A1 METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE EFFICIENT STORE QUEUE USAGE 有权
标题翻译：用于链接更多有效存储队列使用的多个小型存储队列的方法
公开(公告)号：US20090198867A1
公开(公告)日：2009-08-06
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译：数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。响应于第一段不等于第二段，第一个条目链接到第二个条目。

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