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81. 发明申请

US20110018120A1 HIGH-BANDWIDTH RAMP-STACK CHIP PACKAGE 有权
标题翻译：高带宽贴片芯片包装
公开(公告)号：US20110018120A1
公开(公告)日：2011-01-27
申请号：US12507349
申请日：2009-07-22
申请人： Robert J. Drost , James G. Mitchell , David C. Douglas
发明人： Robert J. Drost , James G. Mitchell , David C. Douglas
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/642 , H01L23/645 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/72 , H01L24/90 , H01L25/0652 , H01L29/0657 , H01L2223/6638 , H01L2224/13099 , H01L2224/32145 , H01L2224/32225 , H01L2224/48137 , H01L2224/48157 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/06589 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01067 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/19106 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.
摘要翻译：描述了芯片封装。该芯片封装包括彼此偏移的半导体管芯或芯片堆叠，由此限定具有暴露焊盘的露台。位于大致平行于平台的高带宽斜坡部件电耦合到暴露的焊盘。例如，斜坡部件可以使用：微弹簧，各向异性膜和/或焊料电耦合到半导体管芯。因此，电触点可以具有导电性，电容性或通常的复阻抗。此外，芯片和/或斜面部件可以使用球 - 坑对准技术相对于彼此定位。通过消除对半导体管芯中昂贵且耗费大量的硅通孔（TSV）的需求，芯片封装便于以提供高带宽和低成本的方式堆叠芯片。

82. 发明申请

US20100329607A1 OPTICAL CONNECTOR WITH REDUCED MECHANICAL-ALIGNMENT SENSITIVITY 有权
标题翻译：具有降低机械对准灵敏度的光学连接器
公开(公告)号：US20100329607A1
公开(公告)日：2010-12-30
申请号：US12495228
申请日：2009-06-30
申请人： Robert J. Drost , John E. Cunningham , Ashok V. Krishnamoorthy
发明人： Robert J. Drost , John E. Cunningham , Ashok V. Krishnamoorthy
IPC分类号： G02B6/34 , G02B6/26
CPC分类号： G02B6/4204 , G02B6/30 , G02B6/34 , G02B6/4215 , G02B6/4298 , G02B6/43
摘要： An optical connector is described. This optical connector spatially segregates optical coupling between an optical fiber and an optical component, which relaxes the associated mechanical-alignment requirements. In particular, the optical connector includes an optical spreader component disposed on a substrate. This optical spreader component is optically coupled to the optical fiber at a first coupling region, and is configured to optically couple to the optical component at a second coupling region that is at a different location on the substrate than the first coupling region. Moreover, the first coupling region and the second coupling region are optically coupled by an optical waveguide.
摘要翻译：描述光连接器。该光学连接器在空间上分离光纤和光学部件之间的光学耦合，这松弛了相关的机械对准要求。特别地，光连接器包括设置在基板上的光扩散部件。该光扩散器部件在第一耦合区域光学耦合到光纤，并且被配置为在与第一耦合区域在基板上的不同位置处的第二耦合区域光学耦合到光学部件。此外，第一耦合区域和第二耦合区域通过光波导光学耦合。

83. 发明申请

US20090315157A1 PROTECTION FOR PROXIMITY ELECTRONICS AGAINST ELECTROSTATIC DISCHARGE 有权
标题翻译：针对静电放电的接近电子保护
公开(公告)号：US20090315157A1
公开(公告)日：2009-12-24
申请号：US12144142
申请日：2008-06-23
申请人： Robert J. Drost , Scott M. Fairbanks , Alex Chow
发明人： Robert J. Drost , Scott M. Fairbanks , Alex Chow
IPC分类号： H01L23/62
CPC分类号： H01L25/0657 , H01L23/48 , H01L23/60 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A system of protecting a proximity communication system against electrostatic discharge (ESD). The proximity communication system includes two chips, each having an array of electrical pads at its surface and covered by a thin dielectric layer such that capacitive coupling circuits are formed between the chips when they are joined together. In at least one of the chips, an additional protection pad is formed away from the array, and heavy protection circuitry is connected to it. Its surface is exposed through the dielectric surface over it such that, when an ESD aggressor approaches, the discharge occurs to the protection pad.
摘要翻译：保护接近通信系统免受静电放电（ESD）的系统。接近通信系统包括两个芯片，每个芯片在其表面上具有电焊盘的阵列并被薄的电介质层覆盖，使得当它们连接在一起时，在芯片之间形成电容耦合电路。在至少一个芯片中，附加的保护焊盘远离阵列形成，重保护电路与其连接。其表面通过其上的电介质表面暴露，使得当ESD侵蚀器接近时，放电发生到保护焊盘。

84. 发明申请

US20090279571A1 DIVERSITY PROXIMITY COMMUNICATION 有权
标题翻译：多样性接近通信
公开(公告)号：US20090279571A1
公开(公告)日：2009-11-12
申请号：US12115772
申请日：2008-05-06
申请人： Alex Chow , R. David Hopkins , Robert J. Drost
发明人： Alex Chow , R. David Hopkins , Robert J. Drost
IPC分类号： H04J1/00 , H04J15/00 , H04J13/00 , H04J3/00
CPC分类号： H04B5/0012 , H01L25/0657 , H01L2225/06513 , H01L2225/06531 , H01L2924/0002 , H04B7/04 , H01L2924/00
摘要： A diversity proximity communication system formed on two juxtaposed chips, one having a two-dimensional array of transmit elements, the other having a two-dimensional array of receive elements. The receive and transmit elements need not be aligned and may have nominal alignment of one transmit element overlapping the corners of four receive elements. The elements may be electrical pads capacitively coupled across the interface. Signals of four different multiplexing groups, e.g., time-multiplexed, are supplied to transmitting elements in a 2×2 array. Signals from four receive elements in a 2×2 array are amplified, combined, and demultiplexed for the selected multiplexing group. The gains for the four signals to be combined are differentially controlled to increase the signal-to-noise ratio. The amplification may be determined by the overlap between each of the receive elements and the transmit element of the selected multiplexing group.
摘要翻译：在两个并置芯片上形成的分集接近通信系统，一个具有发射元件的二维阵列，另一个具有接收元件的二维阵列。接收和发送元件不需要对齐，并且可以具有与四个接收元件的角重叠的一个发射元件的标称对准。元件可以是跨接口电容耦合的电焊盘。四个不同复用组的信号，例如时分复用，被提供给2x2阵列中的发射元件。来自2x2阵列中的四个接收元件的信号被放大，组合和解复用用于所选择的复用组。要组合的四个信号的增益被差分控制以增加信噪比。可以通过每个接收元件与所选多路复用组的发送元件之间的重叠来确定放大。

85. 发明授权

US07384804B2 Method and apparatus for electronically aligning capacitively coupled mini-bars 有权
标题翻译：用于电容对齐电容耦合迷你条的方法和装置
公开(公告)号：US07384804B2
公开(公告)日：2008-06-10
申请号：US11125792
申请日：2005-05-09
申请人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
发明人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2224/0401
摘要： One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.
摘要翻译：本发明的一个实施例提供了一种系统，其电子地对准位于面对面的不同半导体芯片上的迷你条，以促进半导体芯片之间通过电容耦合的通信。在操作期间，系统测量第一芯片和第二芯片之间的对准。然后，系统在第一芯片上选择一组发射器迷你条，以基于测量的对准来形成发射机位置。以这种方式，该系统允许将数据信号分配到形成发送器位位置的迷你条并发送。该系统还在第二芯片上选择一组接收器迷你条，以形成基于测量对准的接收器位位置。接下来，系统基于测量的对准将第一芯片上的发射机位位置与第二芯片上的接收器位置相关联。以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

86. 发明授权

US07256628B2 Speed-matching control method and circuit 有权
标题翻译：速度匹配控制方法和电路
公开(公告)号：US07256628B2
公开(公告)日：2007-08-14
申请号：US10671641
申请日：2003-09-26
申请人： Robert J. Drost , William S. Coates , Josephus C. Ebergen
发明人： Robert J. Drost , William S. Coates , Josephus C. Ebergen
IPC分类号： H03L7/06
CPC分类号： G06F1/12
摘要： One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an external frequency signal from a neighboring chip. The system then compares the internal frequency signal with the external frequency signal to generate a control signal, which is applied to the local chip to adjust the operating speed of the local chip, and applied to the internal oscillator to adjust the frequency of the internal oscillator.
摘要翻译：本发明的一个实施例提供了一种匹配本地芯片和相邻芯片之间的异步操作速度的系统。该系统从本地芯片上的内部振荡器得到内部频率信号，并从相邻芯片接收外部频率信号。然后系统将内部频率信号与外部频率信号进行比较，以产生一个控制信号，该控制信号被施加到本地芯片上以调整本地芯片的工作速度，并施加到内部振荡器以调整内部振荡器的频率。

87. 发明授权

US06987412B2 Sense amplifying latch with low swing feedback 有权
标题翻译：具有低摆动反馈的感应放大锁存器
公开(公告)号：US06987412B2
公开(公告)日：2006-01-17
申请号：US10816761
申请日：2004-04-02
申请人： Ivan E. Sutherland , Robert J. Bosnyak , Robert J. Drost
发明人： Ivan E. Sutherland , Robert J. Bosnyak , Robert J. Drost
IPC分类号： H03K3/356 , H03L5/00
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/00013 , H01L2924/0002 , H03K3/037 , H03K17/689 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.
摘要翻译：提出了一种用于锁存和放大电容耦合的芯片间通信信号的系统，其通过接收电容性接收器焊盘上的输入信号并通过反相器馈送输入信号以产生输出信号来操作。输出信号通过弱化逆变器反馈，产生反馈信号，该反馈信号馈送到反相器的输入端，形成输入信号的锁存器。弱化的逆变器被偏置以产生在高偏置电压V H H和低偏压V L之间摆动的反馈信号。 V H设定得比逆变器的切换阈值略高，并且将V L L设定得比切换阈值略低。该反馈信号使得输入信号驻留在接近逆变器的开关阈值的窄电压范围内，从而使得反相器对输入信号中的小转变敏感。

88. 发明授权

US06958538B1 Computer system architecture using a proximity I/O switch 有权
标题翻译：使用接近I / O开关的计算机系统架构
公开(公告)号：US06958538B1
公开(公告)日：2005-10-25
申请号：US10983250
申请日：2004-11-04
申请人： Gary R. Lauterbach , Robert J. Drost
发明人： Gary R. Lauterbach , Robert J. Drost
IPC分类号： H01L23/34 , H02B1/04 , H03L5/00
CPC分类号： G06F15/17375 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.
摘要翻译：本发明的一个实施例提供了一种接近I / O开关，其被配置为在计算机系统中的组件之间传送数据。该接近I / O开关由多个开关芯片组成，它们通过电容耦合耦合在一起。这使得多个开关芯片能够彼此通信，而不受传统的非电容通信机制的限制。接近I / O开关中的多个开关芯片还被配置为通过传统的非电容通信机制与计算机系统中的组件进行通信。

89. 发明授权

US06825708B1 Apparatus and method for an offset-correcting sense amplifier 有权
标题翻译：偏移校正读出放大器的装置和方法
公开(公告)号：US06825708B1
公开(公告)日：2004-11-30
申请号：US10697914
申请日：2003-10-29
申请人： Robert J. Drost , Ivan E. Sutherland
发明人： Robert J. Drost , Ivan E. Sutherland
IPC分类号： G06G712
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H03F1/301 , H03F1/342 , H01L2924/00
摘要： An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.
摘要翻译：一种用于消除偏移电压的感测电路的装置和方法。具体地，在一个实施例中，CMOS反相放大器放大存在于输入节点处的输入信号。电阻反馈电路耦合到CMOS反相放大器，用于消除与CMOS反相放大器相关联的偏移电压。这通过将CMOS反相放大器偏置到其阈值电压来实现。偏置电路耦合到电阻反馈电路，用于在亚阈值导通区域偏置电阻反馈电路中的MOSFET晶体管。因此，电阻反馈电路对输入节点呈现高阻抗。耦合到电阻反馈电路的钳位电路在亚阈值导通区域中保持电阻反馈电路中的晶体管的操作。

90. 发明授权

US06696876B2 Clock interpolation through capacitive weighting 有权
标题翻译：通过电容加权进行时钟插值
公开(公告)号：US06696876B2
公开(公告)日：2004-02-24
申请号：US09759981
申请日：2001-01-12
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
IPC分类号： H03K300
CPC分类号： H03K5/13 , H03K5/08
摘要： A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.
摘要翻译：一种用于设置和控制从多个输入时钟的内插导出的输出时钟的相位的时钟插值电路。通过对多个时钟进行电容加权来执行插值。选择和控制电路提供选择不同电容值以控制加权的能力。还提供了可选的缓冲级，以锐化内插时钟的边沿转换。

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