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81. 发明申请

US20130139032A1 Memory System With Error Detection And Retry Modes Of Operation 有权
公开(公告)号：US20130139032A1
公开(公告)日：2013-05-30
申请号：US13730942
申请日：2012-12-29
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

82. 发明申请

US20130139019A1 Unidirectional Error Code Transfer for Both Read and Write Data Transmitted Via Bidirectional Data Link 有权
标题翻译：通过双向数据链路传输的读取和写入数据的单向错误代码传输
公开(公告)号：US20130139019A1
公开(公告)日：2013-05-30
申请号：US13752324
申请日：2013-01-28
申请人： Yuanlong Wang , Frederick A. Ware
发明人： Yuanlong Wang , Frederick A. Ware
IPC分类号： G06F11/10 , H04L1/08
CPC分类号： G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
摘要翻译：控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。耦合到链路接口的发射机是发送写入数据。延迟元件耦合到编码器的输出。耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

83. 发明申请

US20130132704A1 MEMORY CONTROLLER AND METHOD FOR TUNED ADDRESS MAPPING 审中-公开
标题翻译：用于调谐地址映射的存储器控制器和方法
公开(公告)号：US20130132704A1
公开(公告)日：2013-05-23
申请号：US13813945
申请日：2011-08-29
申请人： Frederick A. Ware
发明人： Frederick A. Ware
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/0292 , G06F12/04 , Y02D10/13
摘要： A memory system maps physical addresses to device addresses in a way that reduces power consumption. The system includes circuitry for deriving efficiency measures for memory usage and selects from among various address-mapping schemes to improve efficiency. The address-mapping schemes can be tailored for a given memory configuration or a specific mixture of active applications or application threads. Schemes tailored for a given mixture of applications or application threads can be applied each time the given mixture is executing, and can be updated for further optimization. Some embodiments mimic the presence of an interfering thread to spread memory addresses across available banks, and thereby reduce the likelihood of interference by later- introduced threads.
摘要翻译：存储系统以减少功耗的方式将物理地址映射到设备地址。该系统包括用于导出用于存储器使用的效率测量的电路，并且从各种地址映射方案中进行选择以提高效率。可以针对给定的存储器配置或活动应用或应用程序线程的特定混合来定制地址映射方案。可以在每次给定混合物执行时为应用程序或应用程序线程定制的方案，并且可以更新以进一步优化。一些实施例模拟存在干扰线程以在可用存储体之间扩展存储器地址，从而降低稍后引入的线程的干扰的可能性。

84. 发明授权

US08441872B2 Memory controller with adjustable width strobe interface 有权
标题翻译：内存控制器带可调宽度选通接口
公开(公告)号：US08441872B2
公开(公告)日：2013-05-14
申请号：US13552511
申请日：2012-07-18
申请人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
发明人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G06F13/4239 , G11C5/02 , G11C5/04 , H05K1/0237 , H05K1/181 , H05K2201/10159 , Y02P70/611
摘要： A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.
摘要翻译：公开了一种在存储器控制器中的操作方法，包括生成模式控制信号以指定第一和第二模式中的至少一个。在第一模式中，存储器控制器被配置为通过发出存储器访问命令来操作，以启动存储器控制器和第一存储器件之间的第一数据传输，并且产生选通信号以伴随与第一数据传输相关联的数据。在第二模式中，控制器被配置为通过发出存储器访问命令来进行操作，以在存储器控制器与包括全宽度的至少第一和第二存储器件之间的第二数据传输中包括第一和第二存储器的数据宽度并且发出伴随与第一和第二存储器设备的每个数据宽度相关联的相应数据传输的第一和第二选通信号。

85. 发明授权

US08432768B2 Mesochronous signaling system with multiple power modes 有权
标题翻译：具有多种功率模式的中间信号系统
公开(公告)号：US08432768B2
公开(公告)日：2013-04-30
申请号：US13132104
申请日：2009-07-09
申请人： Frederick A. Ware , Robert E. Palmer , John W. Poulton
发明人： Frederick A. Ware , Robert E. Palmer , John W. Poulton
IPC分类号： G11C8/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

86. 发明授权

US08412906B2 Memory apparatus supporting multiple width configurations 有权
标题翻译：支持多种宽度配置的内存设备
公开(公告)号：US08412906B2
公开(公告)日：2013-04-02
申请号：US13365890
申请日：2012-02-03
申请人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.
摘要翻译：描述了组织在存储器子部分中并且包括可配置路由以支持多个数据宽度配置的存储器设备。相对窄的宽度配置加载较少的读出放大器，导致相对较窄的存储器配置的功率消耗减少。还描述了将宽度选择信息传送到可配置的存储装置并支持多个宽度配置的点对点数据接口的存储器控制器。

87. 发明授权

US08395951B2 Memory controller 有权
标题翻译：内存控制器
公开(公告)号：US08395951B2
公开(公告)日：2013-03-12
申请号：US13461923
申请日：2012-05-02
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
摘要翻译：一种具有第一和第二接口的存储器组件。提供第一接口以响应于第一时钟信号对地址信息进行采样。第一接口包括在第一时钟信号的时钟周期期间连续地采样地址信息的至少两个比特的输入。提供第二接口以响应于第二时钟信号采样数据，其具有至少是第一时钟信号频率的两倍的频率。第二接口包括在第二时钟信号的时钟周期期间连续采样至少两位数据的输入。

88. 发明申请

US20130032950A1 Techniques for Interconnecting Stacked Dies Using Connection Sites 有权
标题翻译：使用连接站点互连堆叠模块的技术
公开(公告)号：US20130032950A1
公开(公告)日：2013-02-07
申请号：US13641680
申请日：2011-04-13
申请人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
发明人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
IPC分类号： H01L23/48 , H01L21/02
CPC分类号： H01L23/481 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F2213/0038 , H01L25/0657 , H01L25/18 , H01L2224/131 , H01L2224/16146 , H01L2225/06544 , H01L2924/014
摘要： An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
摘要翻译：集成电路管芯包括至少位于其连续区域内的集成电路管芯的表面上的导电连接位置。集成电路还包括位于连续区域外的核心电路。核心电路耦合到至少一个连接位置。

89. 发明授权

US08363493B2 Memory controller having a write-timing calibration mode 有权
公开(公告)号：US08363493B2
公开(公告)日：2013-01-29
申请号：US13544967
申请日：2012-07-09
申请人： Frederick A. Ware
发明人： Frederick A. Ware
IPC分类号： G11C7/10 , G06F12/00
CPC分类号： G11C11/4076 , G06F1/10 , G06F13/1689 , G06F13/4243 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/409 , G11C2207/2254
摘要： A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time.

90. 发明授权

US08359445B2 Method and apparatus for signaling between devices of a memory system 有权
公开(公告)号：US08359445B2
公开(公告)日：2013-01-22
申请号：US12360780
申请日：2009-01-27
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/36
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.

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