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81. 发明授权

US07573102B2 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
标题翻译： ESD保护结构和方法利用高耐压焊盘的基板触发
公开(公告)号：US07573102B2
公开(公告)日：2009-08-11
申请号：US11496490
申请日：2006-08-01
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
摘要翻译：在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

82. 发明申请

US20090108345A1 LDMOS Device and Method of Fabrication 有权
标题翻译： LDMOS器件及其制造方法
公开(公告)号：US20090108345A1
公开(公告)日：2009-04-30
申请号：US12325824
申请日：2008-12-01
申请人： Mu-Yi Liu , Chia-Lun Hsu , Ichen Yang , Kuan-Po Chen , Tao-Cheng Lu
发明人： Mu-Yi Liu , Chia-Lun Hsu , Ichen Yang , Kuan-Po Chen , Tao-Cheng Lu
IPC分类号： H01L29/78
CPC分类号： H01L29/42368 , H01L29/66659 , H01L29/7835 , Y10S438/981
摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.
摘要翻译：提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

83. 发明授权

US06965504B2 ESD protection apparatus and method for a high-voltage input pad 有权
标题翻译：高压输入板的ESD保护装置及方法
公开(公告)号：US06965504B2
公开(公告)日：2005-11-15
申请号：US10304137
申请日：2002-11-26
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Tao-Cheng Lu
IPC分类号： H01L27/02 , H02H3/20
CPC分类号： H01L27/0266 , H01L27/0255
摘要： An ESD protection apparatus for a high-voltage input pad comprises a modulator connected between the input pad and a snapback device with first and second guard rings surrounding the modulator, third guard ring surrounding the snapback device, and first and second guard ring control circuits to control the guard rings such that the protection apparatus has higher triggering and holding voltages under normal operation and lower triggering and holding voltages under ESD event.
摘要翻译：用于高电压输入焊盘的ESD保护装置包括连接在输入焊盘和回弹装置之间的调制器，其具有围绕调制器的第一和第二保护环，围绕着快速恢复装置的第三保护环，以及第一和第二保护环控制电路控制保护环，使保护装置在正常工作状态下具有较高的触发和保持电压，并在ESD事件下具有较低的触发和保持电压。

84. 发明申请

US20050237813A1 Method and system for self-convergent erase in charge trapping memory cells 有权
标题翻译：电荷捕获存储器单元中自会聚擦除的方法和系统
公开(公告)号：US20050237813A1
公开(公告)日：2005-10-27
申请号：US10876255
申请日：2004-06-24
申请人： Nian-Kai Zous , Wen-Jer Tsai , Hung-Yueh Chen , Tao-Cheng Lu
发明人： Nian-Kai Zous , Wen-Jer Tsai , Hung-Yueh Chen , Tao-Cheng Lu
IPC分类号： G11C16/04 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0466 , H01L29/7885 , H01L29/792
摘要： A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.
摘要翻译：提供了用于操作电荷捕获存储器单元的过程和存储器架构。用于操作存储单元的方法包括通过将负电荷注入到电荷俘获结构中来建立高的阈值状态，以设置高状态阈值。该方法包括使用自会聚偏移过程来通过减少电荷俘获结构中的负电荷来为存储器单元建立低阈值状态，以将电池的阈值电压设置为低阈值状态。通过施加包括至少一个偏置脉冲的偏置过程，在存储单元中负电荷减小。偏置脉冲平衡进入和离开电荷捕获层的电荷流，以在期望的阈值水平上实现自会聚。从而避免了过度擦除的情况。

85. 发明授权

US06829125B2 ESD protection circuit for multi-power and mixed-voltage integrated circuit 有权
标题翻译：多功率和混合电压集成电路的ESD保护电路
公开(公告)号：US06829125B2
公开(公告)日：2004-12-07
申请号：US09938511
申请日：2001-08-27
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Sing Su , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Sing Su , Tao-Cheng Lu
IPC分类号： H02H900
CPC分类号： H01L27/0285
摘要： The invention discloses an ESD (Electro Static Discharge) protection circuit, including a resistor device, a capacitor device and a PMOS device. The resistor device is connected in series between a power supply and the capacitor device. The capacitor device is connected in series between the resistor device and the ground. A gate electrode of the PMOS device is connected between the resistor device and the capacitor device. A bulk electrode of the PMOS device is interconnected to a first electrode of the PMOS device, and the first electrode is connected to the power supply. Alternatively, another ESD protection circuit for multiple power supplies includes at least two aforementioned ESD protection circuits, and a common ESD bus. The ESD protection circuits are connected to separate power supplies, and both connected to the common ESD bus. By using the ESD protection circuit, there is no noise between the separate power supplies, and an ESD current could be discharged easily and safely.
摘要翻译：本发明公开了一种ESD（静电放电）保护电路，包括电阻器件，电容器器件和PMOS器件。电阻器件串联在电源和电容器之间。电容器器件串联在电阻器件和地之间。 PMOS器件的栅电极连接在电阻器件和电容器器件之间。 PMOS器件的体电极互连到PMOS器件的第一电极，并且第一电极连接到电源。或者，用于多个电源的另一ESD保护电路包括至少两个上述ESD保护电路和公共ESD总线。 ESD保护电路连接到单独的电源，并且都连接到公共ESD总线。通过使用ESD保护电路，在单独的电源之间不存在噪声，并且ESD电流可以容易且安全地放电。

86. 发明授权

US06791146B2 Silicon controlled rectifier structure with guard ring controlled circuit 有权
标题翻译：具有保护环控制电路的可控硅整流器结构
公开(公告)号：US06791146B2
公开(公告)日：2004-09-14
申请号：US10178235
申请日：2002-06-25
申请人： Chen-Shang Lai , Meng-Huang Liu , Shin Su , Tao-Cheng Lu
发明人： Chen-Shang Lai , Meng-Huang Liu , Shin Su , Tao-Cheng Lu
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L27/0817 , H01L29/7436
摘要： The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.
摘要翻译：本发明提供了具有保护环控制电路的PMSCR（具有第一导电类型的桥接修改的侧向修改的可控硅整流器）。本发明利用诸如开关的控制电路来控制PMSCR保护环的功能。在正常工作中，开关具有低阻抗，使得保护环与阳极短路并收集电子以提高功率跳跃抗扰度。此外，在ESD（静电放电）事件期间，开关具有高阻抗，使得保护环不起作用。因此，具有保护环控制电路的PMSCR可以在HV（高电压）焊盘的应用中增强ESD性能和功率切换抗扰性。

87. 发明授权

US06790730B2 Fabrication method for mask read only memory device 有权
标题翻译：掩模只读存储器件的制造方法
公开(公告)号：US06790730B2
公开(公告)日：2004-09-14
申请号：US10156325
申请日：2002-05-24
申请人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
发明人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L27/11253 , H01L21/26586 , H01L27/112
摘要： A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.
摘要翻译：描述了一种用于掩模只读存储器件的制造方法。该方法提供衬底，并且在衬底上形成掺杂导电层。之后，将掺杂的导电层图案化以形成多个棒状掺杂导电层，随后通过热氧化在基板上和棒状导电层上形成电介质层。多个扩散区同时形成在基板中的棒状导电层的下方。在电介质层上进一步形成图案化的导电层。

88. 发明授权

US06706575B2 Method for fabricating a non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US06706575B2
公开(公告)日：2004-03-16
申请号：US10055265
申请日：2002-01-22
申请人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
发明人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/112 , H01L27/11253 , H01L27/115
摘要： A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.
摘要翻译：描述了制造非易失性存储器的方法。提供其上具有条带堆叠结构的基板。然后在衬底旁边的衬底上形成掩埋漏极，并在掩埋漏极上形成绝缘层。在衬底上顺序形成硅层和覆盖层。然后，在垂直于埋地漏极的方向上连续地对盖层，硅层和条带堆叠结构进行图案化，其中条带层叠结构被图案化成多个栅极。衬底氧化物层形成在栅极，衬底和硅层的暴露表面上。此后，除去盖层，并在硅层的暴露表面上形成金属硅化物层。

89. 发明授权

US06671209B2 Erasing method for p-channel NROM 有权
标题翻译： p沟道NROM的擦除方法
公开(公告)号：US06671209B2
公开(公告)日：2003-12-30
申请号：US10035514
申请日：2001-10-22
申请人： Hung-Sui Lin , Han-Chao Lai , Tao-Cheng Lu
发明人： Hung-Sui Lin , Han-Chao Lai , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/14
摘要： An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.
摘要翻译：用于p沟道氮化物只读存储器的擦除方法。该方法用于具有存储在电荷捕获层中的电荷的p沟道氮化物只读存储器。向控制栅极施加正电压，向漏极施加负电压; 源也是浮动的，n阱是接地的。施加到控制栅极的正电压和到漏极的负电压之间的电压差足以触发带间感应的热电子注入以擦除p沟道氮化物只读存储器。

90. 发明授权

US06665212B1 Reference current generating circuit of multiple bit flash memory 有权
标题翻译：多位闪存的参考电流产生电路
公开(公告)号：US06665212B1
公开(公告)日：2003-12-16
申请号：US10065032
申请日：2002-09-12
申请人： Tso-Hung Fan , Chih-Chieh Yeh , Tao-Cheng Lu
发明人： Tso-Hung Fan , Chih-Chieh Yeh , Tao-Cheng Lu
IPC分类号： G11C1606
CPC分类号： G11C11/5621 , G11C16/30 , G11C2211/5634
摘要： The reference current generation circuit of a multiple bit flash memory. An identical boosted word-line voltage is applied to the gate terminal of reference memory cells in different reference current generation units and a different substrate voltage is applied to the substrate of each reference memory cell so that different reference currents are produced. This arrangement reduces different degree of shifting in the reference currents due to temperature and source voltage Vcc variation.
摘要翻译：多位闪存的参考电流产生电路。将相同的升压字线电压施加到不同参考电流产生单元中的参考存储器单元的栅极端子，并且将不同的衬底电压施加到每个参考存储器单元的衬底，使得产生不同的参考电流。这种布置降低了由于温度和源电压Vcc变化引起的参考电流的不同移位程度。

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