专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US5917752A Nonvolatile semiconductor memory device 失效
公开(公告)号：US5917752A
公开(公告)日：1999-06-29
申请号：US457761
申请日：1995-06-01
申请人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
发明人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
IPC分类号： G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3445 , G11C16/06 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/344 , G11C2216/20
摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

82. 外观设计

USD407327S Watchcase 失效
公开(公告)号：USD407327S
公开(公告)日：1999-03-30
申请号：US80402
申请日：1997-12-08
申请人： Takeshi Wada , Juhei Ozawa
设计人： Takeshi Wada , Juhei Ozawa

83. 外观设计

USD404654S Watchcase 失效
公开(公告)号：USD404654S
公开(公告)日：1999-01-26
申请号：US080021
申请日：1997-11-26
申请人： Toshiaki Kume , Takeshi Wada , Hitoshi Azegami
设计人： Toshiaki Kume , Takeshi Wada , Hitoshi Azegami

84. 外观设计

USD391498S Watchcase 失效
公开(公告)号：USD391498S
公开(公告)日：1998-03-03
申请号：US64399
申请日：1996-12-30
申请人： Toshiaki Kume , Takeshi Wada
设计人： Toshiaki Kume , Takeshi Wada

85. 发明授权

US5544098A Semiconductor memory device having an automatically activated verify function capability 失效
公开(公告)号：US5544098A
公开(公告)日：1996-08-06
申请号：US455152
申请日：1995-05-31
申请人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
发明人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
IPC分类号： G06F12/16 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/12 , G11C29/46 , G11C29/48 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/46 , G11C29/48
摘要： A semiconductor memory device having a plurality of nonvolatile memory devices or elements disposed in a matrix arrangement as one or more memory arrays is provided with a write operation and a verify mode which is automatically implemented when the write operation of the memory device ends. In connection with this, an auto-verify function is set in an internal circuit associated with the memory in accordance with a predetermined control signal and wherein a read mode subsequent to the write operation is implemented. During the auto-verify function, the read mode is implemented by effecting a data comparison circuit, such as an exclusive-OR logic circuit, which performs a coincidence/non-coincidence operation comparing the write data and the read data.

86. 发明授权

US5475692A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5475692A
公开(公告)日：1995-12-12
申请号：US407986
申请日：1995-03-22
申请人： Susumu Hatano , Jun Kitano , Kenji Nishimoto , Shin'ichi Ikenaga , Masayasu Kawamura , Yasushi Takahashi , Takeshi Wada , Michihiro Mishima , Fujio Yamamoto
发明人： Susumu Hatano , Jun Kitano , Kenji Nishimoto , Shin'ichi Ikenaga , Masayasu Kawamura , Yasushi Takahashi , Takeshi Wada , Michihiro Mishima , Fujio Yamamoto
IPC分类号： G11C29/10 , G11C29/14 , G11C29/40 , G06F11/00
CPC分类号： G11C29/40 , G11C29/10 , G11C29/14
摘要： Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.
摘要翻译：这里公开了一种半导体集成电路，用于测试所有位的两种非反相和反相状态的测试数据，其中一种预期数据可以压缩并输出测试结果。半导体集成电路包括：决定电路25，用于决定第一状态，其中由模式寄存器锁存的预期数据和存储单元阵列的读取数据一致;第二状态，读取数据与逻辑反转的预期数据的数据，以及通过异或门以外的第一状态和第二状态的第三状态，以产生能够区分各个状态的2位的信号。这些状态根据高低电平和高阻抗通知到半导体集成电路的外部。

87. 发明授权

US4543711A System for automatically inserting U-tubes of heat exchanger or the like 失效
标题翻译：自动插入热交换器的U型管的系统等
公开(公告)号：US4543711A
公开(公告)日：1985-10-01
申请号：US610409
申请日：1984-05-15
申请人： Takeshi Wada , Hisanao Kita , Tatsuji Wada , Susumu Fujishima , Hironori Kadowaki
发明人： Takeshi Wada , Hisanao Kita , Tatsuji Wada , Susumu Fujishima , Hironori Kadowaki
IPC分类号： B23P21/00 , B23P15/26 , B23P19/02
CPC分类号： B23P19/022 , Y10T29/53039 , Y10T29/53061 , Y10T29/53113 , Y10T29/53117 , Y10T29/53548 , Y10T29/53961 , Y10T29/53974
摘要： Disclosed is a system for automatically successively inserting a plurality of U-shaped heat transfer tubes into holes of support members of an equipment such as a heat exchanger. The system has fixing means for removably fixing the support members such that the corresponding holes of the support members are axially aligned; gripping means adapted to pick up one of the heat transfer tubes and movable to bring the heat transfer tube toward the holes of supporting members; a positioning means disposed between the gripping means and the fixing means and adapted to hold the gripped heat transfer tube horizontally and to make the same align with the holes in the support members; and control means operatively connected to the gripping means and the positioning means so as to sequentially control the operation of both means in a predetermined sequence. The system operates as follows under the control of the control means. The gripping means grips the heat transfer tube and raises the same. The gripping means is then moved toward the support members while the positioning means supports the heat transfer tube. As the heat transfer tube is inserted deeper into the support members, the support of the tube by the positioning means is released. The gripping of the tube by the gripping means is released and the gripping means is then returned to the position for picking up the next tube, after the completion of the insertion of the heat transfer tube.
摘要翻译：公开了一种用于将多个U形传热管自动连续地插入诸如热交换器的设备的支撑构件的孔中的系统。该系统具有用于可拆卸地固定支撑构件的固定装置，使得支撑构件的相应的孔轴向对准; 夹持装置，适于拾取传热管中的一个并且可移动以将传热管朝向支撑构件的孔; 定位装置，设置在夹持装置和固定装置之间，并且适于水平地夹持夹持的传热管并使其与支撑构件中的孔对齐; 以及与所述夹持装置和所述定位装置可操作地连接的控制装置，以便以预定的顺序依次控制两个装置的操作。在控制装置的控制下，该系统如下操作。夹持装置夹紧传热管并提升传热管。然后将夹持装置移动到支撑构件，同时定位装置支撑传热管。当传热管更深地插入支撑构件时，通过定位装置的管的支撑被释放。在完成传热管的插入之后，通过夹持装置夹住管子被释放并且夹紧装置然后返回到用于拾起下一个管子的位置。

88. 发明授权

US4326580A Method of fabricating a structural member by electro slag forming 失效
标题翻译：通过电渣成型制造结构件的方法
公开(公告)号：US4326580A
公开(公告)日：1982-04-27
申请号：US85301
申请日：1979-10-16
申请人： Takeshi Wada , Tetsuo Okuni
发明人： Takeshi Wada , Tetsuo Okuni
IPC分类号： B23K25/00 , B22D27/02
CPC分类号： B23K25/00
摘要： A method of fabricating a structural member such as a wicket gate for water turbines by electro slag forming comprises the steps of mounting a water-cooled metal mold on a part of a previously formed structural member, such as a stem; melting electrodes inserted in the water-cooled metal mold to form the other part of the structural member such as a vane portion of the wicket gate on the previously formed structural member. The previously formed structural member has a concave portion which is exposed in the water-cooled metal mold and the water-cooled metal mold is mounted so as to contact with the previously formed structural member at the lower portion than the top of the concave portion. The previously formed structural member is melted gradually from the central portion of the concave to the outer periphery and then such a portion as the vane portion is formed by molten metal of the electrode.
摘要翻译：通过电渣形成用于水轮机的小门的结构构件的方法包括以下步骤：将水冷金属模安装在预先形成的结构构件（例如杆）的一部分上; 将熔融电极插入水冷金属模具中以形成结构构件的另一部分，例如预先形成的结构构件上的小门的叶片部分。先前形成的结构构件具有暴露在水冷金属模具中的凹部，并且水冷金属模具安装成在比凹部的顶部更低的部分处与先前形成的结构构件接触。先前形成的结构构件从凹部的中心部分逐渐熔化到外周，然后由电极的熔融金属形成叶片部分。

89. 发明授权

US4282448A Monostable multivibrator and FM detector circuit employing common emitter transistor amplifier with plural emitter resistors to avoid circuit operation from signal noise 失效
标题翻译：采用具有多个发射极电阻的公共发射极晶体管放大器的Monostable多谐振荡器和FM检波器电路，以避免信号噪声的电路运行
公开(公告)号：US4282448A
公开(公告)日：1981-08-04
申请号：US969085
申请日：1978-12-13
申请人： Takeshi Wada , Masanori Ienaka , Yasuo Kominami , Yukihiko Miyamoto , Tsuneo Yamada
发明人： Takeshi Wada , Masanori Ienaka , Yasuo Kominami , Yukihiko Miyamoto , Tsuneo Yamada
IPC分类号： H03D3/04 , H03K3/013 , H03K3/02 , H03K3/023 , H03K3/0232 , H03K3/033 , H03K17/16
CPC分类号： H03D3/04 , H03K3/013 , H03K3/023
摘要： This invention discloses a monostable multivibrator which is useful for an FM detector circuit of a pulse count system. The monostable multivibrator has a time constant circuit which includes a capacitor, an amplifier circuit which receives an output of the time constant circuit, a positive feedback circuit which is connected between an output end of the amplifier circuit and an input end of the time constant circuit, and a trigger terminal which is disposed in a circuit loop constructed of the time constant circuit, the amplifier circuit and the positive feedback circuit; and is characterized in that the amplifier circuit is a differential amplifier which is made up of a pair of transistors connected in the differential form, the transistors being connected in common through emitter resistances connected in series with respective emitters thereof. Thus, the monostable multivibrator can provide pulse signals of a fixed pulse width without being influenced by noise.
摘要翻译：本发明公开了一种可用于脉冲计数系统的FM检测器电路的单稳态多谐振荡器。单稳态多谐振荡器具有时间常数电路，其包括电容器，接收时间常数电路的输出的放大器电路，连接在放大器电路的输出端和时间常数电路的输入端之间的正反馈电路以及设置在由时间常数电路，放大电路和正反馈电路构成的电路回路中的触发端子; 并且其特征在于放大电路是由以差分形式连接的一对晶体管构成的差分放大器，晶体管通过与其各自的发射极串联连接的发射极电阻共同连接。因此，单稳态多谐振荡器可以提供固定脉冲宽度的脉冲信号，而不受噪声的影响。

90. 发明授权

US4277703A Monostable multivibrator circuit with clamped non-saturating common emitter amplifier in feedback path 失效
标题翻译：单稳态多谐振荡器电路，在反馈路径中具有钳位非饱和公共发射极放大器
公开(公告)号：US4277703A
公开(公告)日：1981-07-07
申请号：US2108
申请日：1979-01-09
申请人： Takeshi Wada , Masanori Ienaka , Yukihiko Miyamoto , Tsuneo Yamada
发明人： Takeshi Wada , Masanori Ienaka , Yukihiko Miyamoto , Tsuneo Yamada
IPC分类号： H03K3/013 , H03K3/02 , H03K3/023 , H03K3/0232 , H03K5/08 , H03K3/033
CPC分类号： H03K3/023
摘要： This invention relates to a monostable multivibrator which is operated in the non-saturated state. The monostable multivibrator circuit includes a time constant circuit which has a capacitor, an amplifier circuit which receives an output signal of the time constant circuit, a positive feedback circuit which is connected between an output end of the amplifier circuit and an input end of the time constant circuit, and a trigger terminal which is disposed in a circuit loop constructed of the time constant circuit, the amplifier circuit and the positive feedback circuit; and it is characterized in that the positive feedback circuit comprises a signal amplifying transistor which has a base receiving an output of the amplifier circuit and a collector supplying a signal to the time constant circuit, and a level clamp circuit which is coupled to the collector of the transistor in order to hold a collector output potential of the transistor higher than a base input potential thereof.
摘要翻译：本发明涉及在非饱和状态下工作的单稳态多谐振荡器。单稳态多谐振荡器电路包括具有电容器的时间常数电路，接收时间常数电路的输出信号的放大器电路，连接在放大器电路的输出端和时间常数电路的输入端之间的正反馈电路恒定电路和触发端子，其设置在由时间常数电路，放大器电路和正反馈电路构成的电路回路中; 其特征在于，正反馈电路包括信号放大晶体管，其具有接收放大器电路的输出的基极和向时间常数电路提供信号的集电极，以及电平钳位电路，其耦合到该晶体管为了保持晶体管的集电极输出电位高于其基极输入电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式