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81. 发明授权

US5568080A Computational circuit 失效
标题翻译：计算电路
公开(公告)号：US5568080A
公开(公告)日：1996-10-22
申请号：US467827
申请日：1995-06-06
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/063 , G11C27/02 , G06F7/44 , G06G7/16
CPC分类号： G11C27/024 , G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/0635
摘要： A computational circuit that includes a selector for providing an input to one of a plurality of sample/hold circuits. The outputs of the sample/hold circuits are provided to a multiplexer. The output of the multiplexer is provided to a computational portion, such as a multiplier.
摘要翻译：一种计算电路，包括用于向多个采样/保持电路之一提供输入的选择器。采样/保持电路的输出被提供给多路复用器。多路复用器的输出被提供给计算部分，例如乘法器。

82. 发明授权

US5502664A Filter device including SRAM and EEPROM devices 失效
标题翻译：滤波器器件包括SRAM和EEPROM器件
公开(公告)号：US5502664A
公开(公告)日：1996-03-26
申请号：US216826
申请日：1994-03-23
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： H03H15/00 , H03H17/02 , G06F15/31
CPC分类号： H03H17/0291 , H03H15/00
摘要： A filter circuit switches a switching mechanism based on multiplier held in a data register DATA RGST as a digital data, based on the output data of data register DATA RGST, a multiplication circuit M is arranged to have weights corresponding to a capacity of capacitance connected with a common analog input voltage X.
摘要翻译：滤波器电路基于数据寄存器DATA RGST的输出数据，将保持在数据寄存器DATA RGST中的乘法器作为数字数据切换开关机构，乘法电路M被配置为具有对应于与通用模拟输入电压X.

83. 发明授权

US5862070A Discrete cosine transformation circuit 失效
标题翻译：离散余弦变换电路
公开(公告)号：US5862070A
公开(公告)日：1999-01-19
申请号：US820002
申请日：1997-03-18
申请人： Guoliang Shou , Jie Chen , Chanming Zhou , Sunao Takatori
发明人： Guoliang Shou , Jie Chen , Chanming Zhou , Sunao Takatori
IPC分类号： G06F17/14 , G06G7/22 , G06G7/02 , G06G7/19
CPC分类号： G06G7/22 , G06F17/147
摘要： A high-speed discrete cosine transformation circuit includes the one-dimensional input signals x(0) to x(7) being input in parallel to the positive input terminals "+" or the negative input terminals "-" of eight neural operation units (NOU) 11 to 18 through capacitors d0 to d6. In each NOU 11 to 18, input signals x(0) to x(7) are added and subtracted. Input signals x(0) to x(7) are multiplied beforehand by the coefficient in proportion to the capacities of capacitors d0 to d6 which are connected to NOU 11 to 18. Thereafter, discrete cosine transforming coefficients y(0) to y(7) are output. A two-dimensional discrete cosine transformation circuit is realized by using the one-dimensional discrete cosine transforming circuit.
摘要翻译：高速离散余弦变换电路包括与八个神经运算单元的正输入端子“+”或负输入端子“ - ”并联输入的一维输入信号x（0）〜x（7） NOU）11至18通过电容器d0至d6。在每个NOU 11至18中，输入信号x（0）至x（7）被加和减。输入信号x（0）至x（7）预先乘以与连接到NOU 11至18的电容器d0至d6的电容成比例的系数。之后，离散余弦变换系数y（0）至y（7 ）被输出。通过使用一维离散余弦变换电路实现二维离散余弦变换电路。

84. 发明授权

US5708385A Weighted addition circuit 失效
标题翻译：加权加法电路
公开(公告)号：US5708385A
公开(公告)日：1998-01-13
申请号：US657757
申请日：1996-05-31
申请人： Guoliang Shou , Sunao Taktori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Taktori , Makoto Yamamoto
IPC分类号： G06G7/14 , G06G7/42
CPC分类号： G06G7/14
摘要： A weighted addition circuit contains a plurality of resistances, each of which is connected to a common output at one terminal and to different input voltages at the other terminal. The voltage at the common output terminal is a balance voltage of the input resistances. The common output terminal is connected to an amplifier having an odd number of stages of inverters and a feedback resistance connecting the output of the last inverter stage to the input of the first inverter stage. Grounded low pass capacitors and/or balance resistors are also be included in the amplifier to improve the stability of the circuit and prevent undesirable oscillation. Providing a circuit containing a balance voltage of the parallel-connected input resistances allows for precise weighted addition of any number of inputs while still maintaining a small and simple circuit structure.
摘要翻译：加权加法电路包含多个电阻，每个电阻在一个端子处连接到公共输出端，并在另一个端子处连接到不同的输入电压。公共输出端子的电压是输入电阻的平衡电压。公共输出端子连接到具有奇数级的反相器的放大器和将最后的反相器级的输出连接到第一反相器级的输入端的反馈电阻。放大器中还包括接地的低通电容和/或平衡电阻，以提高电路的稳定性并防止不希望的振荡。提供包含并联输入电阻的平衡电压的电路允许精确地加权任意数量的输入，同时仍保持小而简单的电路结构。

85. 发明授权

US06370130B1 Spread spectrum communication system 失效
标题翻译：扩频通信系统
公开(公告)号：US06370130B1
公开(公告)日：2002-04-09
申请号：US09092914
申请日：1998-06-08
申请人： Changming Zhou , Guoliang Shou , Xuping Zhou , Kunihiko Suzuki , Makoto Yamamoto
发明人： Changming Zhou , Guoliang Shou , Xuping Zhou , Kunihiko Suzuki , Makoto Yamamoto
IPC分类号： H04B7216
CPC分类号： H04B1/7077 , H04B1/70735 , H04B1/708 , H04B7/2628 , H04B2201/70702 , H04B2201/7071
摘要： A receiver for spread spectrum communication system receives a traffic channel and common control channel by a plurality of matched filters at least one of which is selectively available for the traffic or the common control channel. At the initial acquisition, a plurality of matched filters are used for receiving the common control channel. At the hand-over, a plurality of matched filters are used to receive traffic channels of the current base station and the base stations in the adjacent cells.
摘要翻译：用于扩频通信系统的接收机通过多个匹配滤波器接收业务信道和公共控制信道，其中至少一个匹配滤波器可选择地可用于业务或公共控制信道。在初始采集时，使用多个匹配滤波器来接收公共控制信道。在切换时，使用多个匹配滤波器来接收当前基站和相邻小区中的基站的业务信道。

86. 发明授权

US5973538A Sensor circuit 失效
标题翻译：传感器电路
公开(公告)号：US5973538A
公开(公告)日：1999-10-26
申请号：US882224
申请日：1997-06-25
申请人： Guoliang Shou , Kazunori Motohashi , Shengmin Lin , Makoto Yamamoto , Toshiyuki Matsumoto , Muneo Harada , Takahiko Ooasa , Yoshihiro Hirota
发明人： Guoliang Shou , Kazunori Motohashi , Shengmin Lin , Makoto Yamamoto , Toshiyuki Matsumoto , Muneo Harada , Takahiko Ooasa , Yoshihiro Hirota
IPC分类号： G01D5/24 , G01D5/16 , G01D5/241 , G06G7/42
CPC分类号： G01D5/24 , G01D5/16 , G01D5/2417
摘要： A small sensor circuit with reducible electric power consumption is formed by connecting inverting amplifiers comprised of CMOS inverters connected in an odd number of stages, in series to guarantee the linearity of the relationship between inputs and outputs, and connecting an impedance as a sensor between the inputs and outputs, or to an input.
摘要翻译：具有可降低功耗的小型传感器电路通过将由奇数级连接的CMOS反相器组成的反相放大器串联连接形成，以确保输入和输出之间的关系线性，并将阻抗作为传感器连接在输入和输出，或输入。

87. 发明授权

US06240148B1 Path-diversity receiving method and system of spread spectrum communication 失效
标题翻译：路径分集接收方法和扩频通信系统
公开(公告)号：US06240148B1
公开(公告)日：2001-05-29
申请号：US08908919
申请日：1997-08-08
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Mamoru Sawahashi , Fumiyuki Adachi
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Mamoru Sawahashi , Fumiyuki Adachi
IPC分类号： H04B710
CPC分类号： H04B7/08 , H04B1/7115 , H04B2201/70701
摘要： The present invention provides a path-diversity system featuring a small-size phase compensating circuit. This circuit calculates a compensating coefficient according to the signals of a pilot block or a pair of pilot blocks surrounding an information block, and then compensates information signals thereafter by the calculated compensating coefficient.
摘要翻译：本发明提供一种具有小尺寸相位补偿电路的路径分集系统。该电路根据导频块或围绕信息块的一对导频块的信号来计算补偿系数，然后通过计算的补偿系数补偿信息信号。

88. 发明授权

US6122654A Complex multiplication circuit 失效
标题翻译：复数乘法电路
公开(公告)号：US6122654A
公开(公告)日：2000-09-19
申请号：US66540
申请日：1998-04-27
申请人： Changming Zhou , Xuping Zhou , Guoliang Shou
发明人： Changming Zhou , Xuping Zhou , Guoliang Shou
IPC分类号： G06F17/10 , G06F17/16 , G06G7/22 , H03F1/34 , H03H15/00 , H03H17/02 , G06F7/52
CPC分类号： G06G7/22
摘要： A complex multiplication circuit of a calculation formula equivalent but different from the usual formula.The calculation formula is as follows:Pr={x(a+b)-b(x+y)} equivalent to (ax-by)Pi={y(a-b)+b(x+y)} equivalent to (ay+bx)Here,Input signal: x+jyMultiplier:a+jbMultiplication result:Pr+jPi.
摘要翻译：计算公式的复乘法电路等效但不同于通常的公式。计算公式如下：等价于（ay）的（ax-by）Pi = {y（ab）+ b（x + y）}的Pr = {x（a + b）-b（x + y） + bx）这里，输入信号：x + jy乘数：a + jb乘法结果：Pr + jPi。

89. 发明授权

US6073149A Computational circuit 失效
标题翻译：计算电路
公开(公告)号：US6073149A
公开(公告)日：2000-06-06
申请号：US60000
申请日：1998-04-15
申请人： Guoliang Shou , Kazunori Motohashi , Ying Chen , Takashi Tomatsu , Changming Zhou , Jie Chen
发明人： Guoliang Shou , Kazunori Motohashi , Ying Chen , Takashi Tomatsu , Changming Zhou , Jie Chen
IPC分类号： G06F7/49 , G06J1/00 , G06F7/00 , G06G7/00
CPC分类号： G06F7/49 , G06F2207/386
摘要： A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and thresholding circuits in the above quantizing portion consist of voltage-driven circuits including capacitive couplings.
摘要翻译：一种用于多值附加的计算电路，包括并行加法器，输出加法器，量化部分和逻辑转换部分。上述量化部分中的上述加法器和阈值电路中的加法电路由包括电容耦合的电压驱动电路组成。

90. 发明授权

US5892266A Layout structure of capacitive element(s) and interconnections in a semiconductor 失效
标题翻译：半导体中的电容元件和互连的布局结构
公开(公告)号：US5892266A
公开(公告)日：1999-04-06
申请号：US865442
申请日：1997-05-30
申请人： Yoshihiro Hirota , Toshiyuki Matsumoto , Guoliang Shou , Kazunori Motohashi
发明人： Yoshihiro Hirota , Toshiyuki Matsumoto , Guoliang Shou , Kazunori Motohashi
IPC分类号： H01L21/768 , H01L21/822 , H01L23/522 , H01L27/04 , H01L27/08 , H01L29/41
CPC分类号： H01L27/0805 , Y10S257/919
摘要： The present invention reduces parasitic capacitance in a capacitive element distribution system by running unit electrode lead lines and common electrode lead lines in different directions so that the conductor lines may be sufficiently separated to suppress parasitic capacitance.
摘要翻译：本发明通过在不同方向上运行单元电极引线和公共电极引线来减小电容元件分配系统中的寄生电容，使得导体线可以被充分地分离以抑制寄生电容。

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