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1. 再颁专利

USRE37953E1 Filter circuit for communication 失效
标题翻译：滤波电路进行通讯
公开(公告)号：USRE37953E1
公开(公告)日：2002-12-31
申请号：US09404783
申请日：1999-09-24
申请人： Guoliang Shou , Chanming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
发明人： Guoliang Shou , Chanming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
IPC分类号： G06G702
CPC分类号： H03H17/0254 , H03H11/04 , H04B1/7093
摘要： The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.
摘要翻译：本发明的目的是提供一种用于通信生成有效数字输出的滤波器电路以及低功耗滤波电路中的模拟输出。根据通过在采集之后对信号进行部分采样可以执行峰值检测的经验，间歇地保持模拟输出信号，使A / D转换电路的功能速度最小化。

2. 发明授权

US06252899B1 Complex despreading system 失效
标题翻译：复杂解扩系统
公开(公告)号：US06252899B1
公开(公告)日：2001-06-26
申请号：US09055346
申请日：1998-04-06
申请人： Chanming Zhou , Guoliang Shou
发明人： Chanming Zhou , Guoliang Shou
IPC分类号： H04L2730
CPC分类号： H04B1/7093
摘要： A compact and easily-assembled circuit for a complex despreading system, arranged such that the circuit does not contain pairs of adders at the output area. The configuration of the circuit enables the addition and subtraction of different signal components to occur before the multiplication stage and not at a pair of adders located at the output area The complex despreader system employs a complex matched filter at a receiver for despreading received signals with a QPSK system in the primary modulation and a BPSK system in the secondary modulation modulated at a transmitter. The input area of each matched filter of I and Q channels includes a pair of adders. One adder generates a first signal having a positive in-phase and a positive quadrature component. The other adder generates a second signal having a negative in-phase component and a positive quadrature component. Next, an I-channel multiplication circuit multiplies both components of the first signal by a spread code then adds the multiplication results together. Likewise, a Q-channel multiplication and addition circuit multiplies the components of the second signal by a spread code and then adds the multiplication results together.
摘要翻译：一种用于复杂解扩系统的紧凑且容易组装的电路，其布置成使得该电路在输出区域不包含加法器对。电路的配置使得不同信号分量的相加和减法在乘法阶段之前发生，而不是在位于输出区的一对加法器处。复数解扩器系统在接收机处采用复匹配滤波器来解扩接收信号一次调制中的QPSK系统和在发射机调制的二次调制中的BPSK系统。 I和Q通道的每个匹配滤波器的输入区域包括一对加法器。一个加法器产生具有正同相和正正交分量的第一信号。另一个加法器产生具有负同相分量和正正交分量的第二信号。接下来，I信道乘法电路将第一信号的两个分量乘以扩展码，然后将乘法结果相加。同样，Q信道乘法和加法电路将第二信号的分量乘以扩展码，然后将相乘结果相加。

3. 发明授权

US5862070A Discrete cosine transformation circuit 失效
标题翻译：离散余弦变换电路
公开(公告)号：US5862070A
公开(公告)日：1999-01-19
申请号：US820002
申请日：1997-03-18
申请人： Guoliang Shou , Jie Chen , Chanming Zhou , Sunao Takatori
发明人： Guoliang Shou , Jie Chen , Chanming Zhou , Sunao Takatori
IPC分类号： G06F17/14 , G06G7/22 , G06G7/02 , G06G7/19
CPC分类号： G06G7/22 , G06F17/147
摘要： A high-speed discrete cosine transformation circuit includes the one-dimensional input signals x(0) to x(7) being input in parallel to the positive input terminals "+" or the negative input terminals "-" of eight neural operation units (NOU) 11 to 18 through capacitors d0 to d6. In each NOU 11 to 18, input signals x(0) to x(7) are added and subtracted. Input signals x(0) to x(7) are multiplied beforehand by the coefficient in proportion to the capacities of capacitors d0 to d6 which are connected to NOU 11 to 18. Thereafter, discrete cosine transforming coefficients y(0) to y(7) are output. A two-dimensional discrete cosine transformation circuit is realized by using the one-dimensional discrete cosine transforming circuit.
摘要翻译：高速离散余弦变换电路包括与八个神经运算单元的正输入端子“+”或负输入端子“ - ”并联输入的一维输入信号x（0）〜x（7） NOU）11至18通过电容器d0至d6。在每个NOU 11至18中，输入信号x（0）至x（7）被加和减。输入信号x（0）至x（7）预先乘以与连接到NOU 11至18的电容器d0至d6的电容成比例的系数。之后，离散余弦变换系数y（0）至y（7 ）被输出。通过使用一维离散余弦变换电路实现二维离散余弦变换电路。

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