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81. 发明授权

US08467253B2 Reading memory elements within a crossbar array 有权
公开(公告)号：US08467253B2
公开(公告)日：2013-06-18
申请号：US12786073
申请日：2010-05-24
申请人： Frederick Perner
发明人： Frederick Perner
IPC分类号： G11C7/10
CPC分类号： G11C7/062 , G11C5/063 , G11C7/067 , G11C8/10 , G11C13/0002 , G11C13/004 , G11C27/02 , G11C2013/0045 , G11C2013/0057 , G11C2207/063 , G11C2213/77
摘要： A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric current sensed from the target memory element when the target memory element is fully selected.

82. 发明申请

US20120057390A1 MEMORY ARRAY WITH WRITE FEEDBACK 有权
标题翻译：记忆阵列与写反馈
公开(公告)号：US20120057390A1
公开(公告)日：2012-03-08
申请号：US12875423
申请日：2010-09-03
申请人： Wei Yi , Frederick Perner , Matthew D. Pickett , Muhammed Shakeel Qureshi
发明人： Wei Yi , Frederick Perner , Matthew D. Pickett , Muhammed Shakeel Qureshi
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C8/08 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/0076 , G11C2211/5624 , G11C2213/77
摘要： A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.
摘要翻译：具有写入反馈的存储器阵列包括与多条列线相交的许多行线，连接在行线之一和列线之一之间的存储元件，选择性地施加到行线之一的电气供应 ; 以及用于控制由电气供应提供的电气状况的反馈控制回路。用于设置存储器阵列内的存储元件的状态的方法包括将电气条件施加到存储器阵列内的存储元件，感测存储元件的电阻状态，以及基于所感测的电阻状态来控制电气状态，从而导致记忆元件达到目标电阻。

83. 发明申请

US20060288059A1 Synchronous counting circuit 有权
标题翻译：同步计数电路
公开(公告)号：US20060288059A1
公开(公告)日：2006-12-21
申请号：US11155523
申请日：2005-06-16
申请人： Frederick Perner
发明人： Frederick Perner
IPC分类号： G06F15/00
CPC分类号： H03K23/00
摘要： A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to sequentially count out a selected word of data from the M by N register. The present design replaces a single counter latch circuit with a plurality or stack of selectable latches and employs combined load/store logic and counter controls.
摘要翻译：提供了一个用于高级应用的M位N位同步计数器。 M比特N位同步计数器包括M比特N寄存器，被配置为接收和存储对应于与被配置为从M×N寄存器顺序排列所选择的数据字的N位计数器集成的至少一个字的数据。本设计用单个计数器锁存电路代替多个或堆叠的可选择的锁存器，并采用组合的加载/存储逻辑和计数器控制。

84. 发明申请

US20060238217A1 Active interconnects and control points in integrated circuits 有权
标题翻译：集成电路中的有源互连和控制点
公开(公告)号：US20060238217A1
公开(公告)日：2006-10-26
申请号：US11112795
申请日：2005-04-21
申请人： R. Williams , Philip Kuekes , Frederick Perner , Greg Snider , Duncan Stewart
发明人： R. Williams , Philip Kuekes , Frederick Perner , Greg Snider , Duncan Stewart
IPC分类号： H03K19/003
CPC分类号： H05K7/1092 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.
摘要翻译：在本发明的各种实施例中，在集成电路的互连层处引入可调电阻器，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或者在制造后配置集成电路的装置。例如，当诸如晶体管的某些内部组件由于制造缺陷而没有指定的电子特性时，可以使用根据本发明的实施例的包括在集成电路的互连层中的可调电阻器的可变电阻的调整以调整内部电压和/或电平以便改善有缺陷的部件。在其他情况下，可调谐电阻器可以用作开关以配置集成电路部件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。在某些情况下，可能会关闭组件和模块，而在其他情况下，可能会打开组件和模块。

85. 发明申请

US20060017875A1 Method of making active matrix display 失效
标题翻译：制作有源矩阵显示的方法
公开(公告)号：US20060017875A1
公开(公告)日：2006-01-26
申请号：US10897533
申请日：2004-07-23
申请人： Frederick Perner , Krzysztof Nauka
发明人： Frederick Perner , Krzysztof Nauka
IPC分类号： G02F1/1335 , G02F1/1343
CPC分类号： G02F1/1362 , G02F1/133305 , G02F1/1368 , G02F2001/136295
摘要： A method of making a lower cost active matrix display. In a particular embodiment, the method includes providing at least one first conductor upon a substrate and depositing a gate dielectric upon the first conductor and substrate. At least one paired second conductor and a pixel electrode are deposited upon the gate dielectric, with the second conductor crossing the first conductor and with a narrow gap between the paired second conductor and the pixel electrode. A semiconductor material is deposited over the paired second conductor and pixel electrode, filling the narrow gap. The narrow gap shelters a portion of the semiconductor material, which serves as a semiconductor bridge capable of functioning either as an insulator or as a channel region of a field effect transistor. The remaining, unsheltered semiconductor material is removed. A liquid crystal layer is then deposited upon the paired second conductor, the pixel electrode and the sheltered semiconductor material, and a translucent conductor is deposited upon the liquid crystal display layer. An associated display is also provided
摘要翻译：制作成本较低的有源矩阵显示的方法。在特定实施例中，该方法包括在衬底上提供至少一个第一导体并在第一导体和衬底上沉积栅极电介质。至少一对成对的第二导体和像素电极沉积在栅极电介质上，其中第二导体与第一导体交叉并且在成对的第二导体和像素电极之间具有窄间隙。半导体材料沉积在成对的第二导体和像素电极上，填充窄间隙。窄间隙避开半导体材料的一部分，其用作能够用作场效应晶体管的绝缘体或沟道区的半导体桥。剩余的未加帽的半导体材料被去除。然后将液晶层沉积在成对的第二导体，像素电极和遮蔽半导体材料上，并且半透明导体沉积在液晶显示层上。还提供了相关联的显示

86. 发明授权

US06987692B2 Magnetic memory having angled third conductor 有权
标题翻译：具有成角度的第三导体的磁存储器
公开(公告)号：US06987692B2
公开(公告)日：2006-01-17
申请号：US10678555
申请日：2003-10-03
申请人： Kenneth K. Smith , Frederick Perner
发明人： Kenneth K. Smith , Frederick Perner
IPC分类号： G11C11/15
CPC分类号： G11C5/063 , G11C11/16
摘要： One embodiment of a magnetic memory includes a magnetic memory stack and a first line adjacent the magnetic memory stack. A second line crosses the first line, and a third line crosses the first line and the second line. The third line is angled relative to the first line and the second line, where the first line, the second line and the third line are configured to produce magnetic fields that set states of the magnetic memory stack.
摘要翻译：磁存储器的一个实施例包括磁存储器堆叠和与磁存储器堆叠相邻的第一行。第二行穿过第一行，第三行穿过第一行和第二行。第三线相对于第一线和第二线成角度，其中第一线，第二线和第三线被配置成产生设定磁存储器堆叠状态的磁场。

87. 发明申请

US20050254292A1 Magnetic memory device 有权
标题翻译：磁存储器件
公开(公告)号：US20050254292A1
公开(公告)日：2005-11-17
申请号：US10843787
申请日：2004-05-11
申请人： Thomas Anthony , Frederick Perner , Heon Lee , Robert Walmsley
发明人： Thomas Anthony , Frederick Perner , Heon Lee , Robert Walmsley
IPC分类号： G11C11/14 , G11C11/16
CPC分类号： G11C11/16 , G11C11/1675
摘要： The present invention provides a magnetic memory device that includes a magnetic memory cell switchable between two states by the application of a magnetic field wherein the magnetic field for such switching is dependent in part on a memory cell temperature. The device further includes at least one heater element proximate to the magnetic memory cell and series connected with the magnetic memory cell for heating of the magnetic memory cell. The device also includes a circuit for selectively applying the electrical current through the at least one heater element so as to heat the cell and facilitate cell state-switching.
摘要翻译：本发明提供了一种磁存储器件，其包括通过施加磁场在两个状态之间切换的磁存储器单元，其中用于这种切换的磁场部分地取决于存储单元温度。该装置还包括靠近磁存储器单元的至少一个加热器元件，并且与磁存储单元连接的用于加热磁存储单元的串联。该装置还包括用于选择性地施加电流通过至少一个加热器元件以便加热电池并促进电池状态切换的电路。

88. 发明申请

US20050237845A1 Data storage device and method of forming the same 有权
标题翻译：数据存储装置及其形成方法
公开(公告)号：US20050237845A1
公开(公告)日：2005-10-27
申请号：US11171694
申请日：2005-06-30
申请人： Frederick Perner , Andrew Van Brocklin , Warren Jackson
发明人： Frederick Perner , Andrew Van Brocklin , Warren Jackson
IPC分类号： G11C11/15 , G11C8/00 , G11C8/08 , G11C11/14 , G11C11/16 , G11C17/00 , H01L27/22 , H01L27/24
CPC分类号： G11C11/16 , G11C8/08 , G11C13/0028 , G11C13/003 , G11C2213/72 , G11C2213/78 , H01L27/224 , H01L27/24
摘要： A resistive cross point memory cell array comprising a plurality of word lines, a plurality of bit lines, a plurality of cross points formed by the word lines and the bit lines, and a plurality of memory cells, each of the memory cells being located at a different one of the cross points, wherein a first bit line comprises a distributed series diode along an entire length of the bit line such that each of the associated memory cells located along the first bit line is coupled between the distributed series diode and an associated word line.
摘要翻译：一种电阻交叉点存储单元阵列，包括多个字线，多个位线，由字线和位线形成的多个交叉点，以及多个存储单元，每个存储器单元位于交叉点中的不同的一个，其中第一位线包括沿着位线的整个长度的分布式串联二极管，使得沿着第一位线定位的每个相关联的存储器单元耦合在分布式串联二极管和相关联的字线。

89. 发明申请

US20050169059A1 Current threshold detector 有权
标题翻译：电流阈值检测器
公开(公告)号：US20050169059A1
公开(公告)日：2005-08-04
申请号：US10767428
申请日：2004-01-29
申请人： Frederick Perner , Manoj Bhattacharyya
发明人： Frederick Perner , Manoj Bhattacharyya
IPC分类号： G11C11/15 , G11C5/00 , G11C7/00 , G11C11/16 , G11C29/00 , H01L21/8246 , H01L27/105
CPC分类号： G11C11/1673 , G11C11/1675 , G11C29/021 , G11C29/028 , G11C29/24 , G11C29/50008 , G11C2029/5002 , G11C2029/5006
摘要： A magnetic memory cell write current threshold detector. The magnetic memory cell write current threshold detector includes a first MRAM test cell receiving a write current and sensing when the write current exceeds a first threshold, and a second MRAM test cell receiving the write current and sensing when the write current exceeds a second threshold.
摘要翻译：磁存储单元写入电流阈值检测器。磁存储单元写入电流阈值检测器包括第一MRAM测试单元，其接收写入电流并检测写入电流是否超过第一阈值;以及第二MRAM测试单元接收写入电流并感测写入电流超过第二阈值时。

90. 发明申请

US20050117412A1 Selecting a magnetic memory cell write current 有权
公开(公告)号：US20050117412A1
公开(公告)日：2005-06-02
申请号：US11003904
申请日：2004-12-03
申请人： Frederick Perner
发明人： Frederick Perner
IPC分类号： G11C11/15 , G11C7/04 , G11C7/22 , G11C11/00 , G11C11/02 , G11C11/16 , G11C29/00 , H01L21/8246 , H01L27/105
CPC分类号： G11C11/16
摘要： The invention includes an apparatus and method for selecting a desirable magnitude of a magnetic memory cell write current. The method includes determining a minimal magnitude of write current for writing to the magnetic memory cell, determining a maximal magnitude of write current for writing to the magnetic memory cell, and calculating the selected magnitude of magnetic memory cell write current based on the minimal magnitude of write current and the maximal magnitude of write current.

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