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81. 发明授权

US07390701B2 Method of forming a digitalized semiconductor structure 失效
标题翻译：形成数字化半导体结构的方法
公开(公告)号：US07390701B2
公开(公告)日：2008-06-24
申请号：US11087781
申请日：2005-03-23
申请人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri Antoniadis
发明人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri Antoniadis
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/78687
摘要： A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.
摘要翻译：多栅极FET结构包括半导体衬底。在半导体衬底上形成栅区。栅极区域包括栅极部分和沟道部分。栅极部分具有与通道部分相邻的至少两个相对的垂直表面。源极区域在一端邻接栅极区域，漏极扩散区域在另一端邻接栅极区域。

82. 发明授权

US07250359B2 Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization 有权
标题翻译：使用梯度GeSi层和平面化控制Si中Ge中的穿透位错密度
公开(公告)号：US07250359B2
公开(公告)日：2007-07-31
申请号：US10022689
申请日：2001-12-17
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L21/20
CPC分类号： H01L21/02505 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , Y10S438/933
摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.
摘要翻译：一种半导体结构，包括半导体衬底，在衬底上的至少一个第一晶体外延层，第一层具有被平坦化的表面，以及在至少一个第一层上的至少一个第二晶体外延层。在本发明的另一个实施例中，提供了包括硅衬底和在硅衬底上生长的GeSi分级区域的半导体结构，压缩应变被并入渐变区域以抵消在热处理期间结合的拉伸应变。在本发明的另一个实施例中，提供了一种半导体结构，其包括半导体衬底，具有在衬底上生长的渐变区域的第一层，压缩应变结合在渐变区域中以抵消在热处理期间结合的拉伸应变，所述第一层具有平坦化的表面，以及设置在所述第一层上的第二层。在本发明的另一个实施例中，提供了一种制造半导体结构的方法，包括提供半导体衬底，在衬底上提供至少一个第一晶体外延层，并平坦化第一层的表面。

83. 发明授权

US07081410B2 Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization 失效
公开(公告)号：US07081410B2
公开(公告)日：2006-07-25
申请号：US10826156
申请日：2004-04-16
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L21/302
CPC分类号： H01L21/02505 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , Y10S438/933
摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

84. 发明授权

US06974735B2 Dual layer Semiconductor Devices 有权
标题翻译：双层半导体器件
公开(公告)号：US06974735B2
公开(公告)日：2005-12-13
申请号：US10216085
申请日：2002-08-09
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L21/8238 , H01L29/10 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/1054 , Y10S438/933
摘要： A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer supports at least a portion of electron conduction for at least one n-channel component. The proximal layer has a thickness that permits a hole wave function to effectively extend from the proximal layer into the distal layer to facilitate hole conduction by the distal layer. A method for fabricating a semiconductor-based device includes providing a distal portion of a channel layer and providing a proximal portion of the channel layer.
摘要翻译：基于半导体的器件包括沟道层，其包括远端层和与远端层接触的近端层。远端层支撑至少一个p沟道分量的至少一部分空穴传导，并且近端支撑至少一个n沟道分量的至少一部分电子传导。近端层具有允许空穴波函数从近端层有效地延伸到远侧层中的厚度，以便于远端层的空穴传导。一种用于制造基于半导体的器件的方法包括提供沟道层的远端部分并提供沟道层的近端部分。

85. 发明授权

US06927147B2 Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates 失效
标题翻译：晶格失配的半导体与硅通过晶片键合虚拟衬底的共面整合
公开(公告)号：US06927147B2
公开(公告)日：2005-08-09
申请号：US10603850
申请日：2003-06-25
申请人： Eugene A. Fitzgerald , Arthuer J. Pitera
发明人： Eugene A. Fitzgerald , Arthuer J. Pitera
IPC分类号： H01L21/20 , H01L21/762 , H01L21/30
CPC分类号： H01L21/76254 , H01L21/2007 , H01L21/76256 , Y10T428/25
摘要： A method of bonding lattice-mismatched semiconductors is provided. The method includes forming a Ge-based virtual substrate and depositing on the virtual substrate a CMP layer that forms a planarized virtual substrate. Also, the method includes bonding a Si substrate to the planarized virtual substrate and performing layer exfoliation on selective layers of the planarized virtual substrate producing a damaged layer of Ge. Furthermore, the method includes removing the damaged layer of Ge.
摘要翻译：提供了结合晶格失配的半导体的方法。该方法包括形成Ge基虚拟衬底并在虚拟衬底上沉积形成平坦化虚拟衬底的CMP层。此外，该方法包括将Si衬底接合到平坦化虚拟衬底并且在平坦化的虚拟衬底的选择层上进行层剥离，产生损伤的Ge层。此外，该方法包括去除损坏的Ge层。

86. 发明授权

US06916727B2 Enhancement of P-type metal-oxide-semiconductor field effect transistors 失效
标题翻译： P型金属氧化物半导体场效应晶体管的增强
公开(公告)号：US06916727B2
公开(公告)日：2005-07-12
申请号：US10177571
申请日：2002-06-21
申请人： Christopher W. Leitz , Minjoo L. Lee , Eugene A. Fitzgerald
发明人： Christopher W. Leitz , Minjoo L. Lee , Eugene A. Fitzgerald
IPC分类号： H01L21/20 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/80
CPC分类号： H01L29/1054 , H01L21/823807 , H01L27/092 , H01L29/802
摘要： A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.
摘要翻译：一种结构包括设置在基底上的拉伸应变层，拉伸应变层具有第一厚度。压缩层设置在拉伸应变层和基底之间，压缩层具有第二厚度。选择第一和第二厚度以限定拉伸应变层中的第一载流子迁移率和压缩层中的第二载流子迁移率。

87. 发明授权

US06876010B1 Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization 失效
标题翻译：使用梯度GeSi层和平面化控制Si中Ge中的穿透位错密度
公开(公告)号：US06876010B1
公开(公告)日：2005-04-05
申请号：US09611024
申请日：2000-07-06
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L21/20 , H01L31/072
CPC分类号： H01L21/02505 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , Y10S438/933
摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.
摘要翻译：一种半导体结构，包括半导体衬底，在衬底上的至少一个第一晶体外延层，第一层具有被平坦化的表面，以及在至少一个第一层上的至少一个第二晶体外延层。在本发明的另一个实施例中，提供了包括硅衬底和在硅衬底上生长的GeSi分级区域的半导体结构，压缩应变被并入渐变区域以抵消在热处理期间结合的拉伸应变。在本发明的另一个实施例中，提供了一种半导体结构，其包括半导体衬底，具有在衬底上生长的渐变区域的第一层，压缩应变结合在渐变区域中以抵消在热处理期间结合的拉伸应变，所述第一层具有平坦化的表面，以及设置在所述第一层上的第二层。在本发明的另一个实施例中，提供了一种制造半导体结构的方法，包括提供半导体衬底，在衬底上提供至少一个第一晶体外延层，并平坦化第一层的表面。

88. 发明授权

US06805744B2 Method of producing device quality (Al)InGaP alloys on lattice-mismatched substrates 失效
标题翻译：在晶格失配衬底上生产器件质量（Al）InGaP合金的方法
公开(公告)号：US06805744B2
公开(公告)日：2004-10-19
申请号：US10023047
申请日：2001-12-13
申请人： Andrew Y. Kim , Eugene A. Fitzgerald
发明人： Andrew Y. Kim , Eugene A. Fitzgerald
IPC分类号： C30B2506
CPC分类号： H01L21/02392 , C30B25/02 , C30B29/40 , H01L21/02395 , H01L21/02461 , H01L21/02505 , H01L21/0251 , H01L21/02543 , H01L21/02576 , H01L21/0262 , H01L31/1844 , H01L33/0062 , H01L33/0066 , H01L33/30 , Y02E10/544
摘要： A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1−y)1−xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.
摘要翻译：一种形成半导体结构的方法，包括提供GaP的单晶半导体衬底，以及制造包括多个外延半导体In x（Al y Ga 1-y）1-xP合金层的渐变组合物缓冲层。缓冲器包括立即接触基板的第一合金层，其具有与基板的晶格常数几乎相同的晶格常数，随后的合金层具有不同于相邻层的晶格常数小于1％，以及具有晶格的最终合金层基本上不同于基底的常数。最终合金层的生长温度比第一合金层的生长温度低至少20℃。

89. 发明授权

US06737670B2 Semiconductor substrate structure 失效
公开(公告)号：US06737670B2
公开(公告)日：2004-05-18
申请号：US10384160
申请日：2003-03-07
申请人： Zhi-Yuan Cheng , Eugene A. Fitzgerald , Dimitri A. Antoniadis , Judy L. Hoyt
发明人： Zhi-Yuan Cheng , Eugene A. Fitzgerald , Dimitri A. Antoniadis , Judy L. Hoyt
IPC分类号： H01L2906
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02546 , Y10S438/933
摘要： A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

90. 发明授权

US06730551B2 Formation of planar strained layers 失效
标题翻译：平面应变层的形成
公开(公告)号：US06730551B2
公开(公告)日：2004-05-04
申请号：US10211126
申请日：2002-08-02
申请人： Minjoo L. Lee , Christopher W. Leitz , Eugene A. Fitzgerald
发明人： Minjoo L. Lee , Christopher W. Leitz , Eugene A. Fitzgerald
IPC分类号： H01L21337
CPC分类号： H01L29/1054 , H01L21/823807 , H01L27/092 , H01L29/78 , H01L29/802
摘要： A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.
摘要翻译：一种用于形成结构的结构和方法，所述方法包括形成压缩应变半导体层，所述压应变层具有大于或等于0.25％的应变。在压缩应变层上形成拉伸应变半导体层。压缩应变层基本上是平面的，具有表面粗糙度，其特征在于：（i）平均波长大于压缩应变层中的载体的平均波长或（ii）平均高度小于10nm。

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