专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06927147B2 Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates 失效
标题翻译：晶格失配的半导体与硅通过晶片键合虚拟衬底的共面整合
公开(公告)号：US06927147B2
公开(公告)日：2005-08-09
申请号：US10603850
申请日：2003-06-25
申请人： Eugene A. Fitzgerald , Arthuer J. Pitera
发明人： Eugene A. Fitzgerald , Arthuer J. Pitera
IPC分类号： H01L21/20 , H01L21/762 , H01L21/30
CPC分类号： H01L21/76254 , H01L21/2007 , H01L21/76256 , Y10T428/25
摘要： A method of bonding lattice-mismatched semiconductors is provided. The method includes forming a Ge-based virtual substrate and depositing on the virtual substrate a CMP layer that forms a planarized virtual substrate. Also, the method includes bonding a Si substrate to the planarized virtual substrate and performing layer exfoliation on selective layers of the planarized virtual substrate producing a damaged layer of Ge. Furthermore, the method includes removing the damaged layer of Ge.
摘要翻译：提供了结合晶格失配的半导体的方法。该方法包括形成Ge基虚拟衬底并在虚拟衬底上沉积形成平坦化虚拟衬底的CMP层。此外，该方法包括将Si衬底接合到平坦化虚拟衬底并且在平坦化的虚拟衬底的选择层上进行层剥离，产生损伤的Ge层。此外，该方法包括去除损坏的Ge层。

2. 发明授权

US08586452B2 Methods for forming semiconductor device structures 有权
公开(公告)号：US08586452B2
公开(公告)日：2013-11-19
申请号：US13227077
申请日：2011-09-07
申请人： Anthony J. Lochtefeld , Thomas A. Langdo , Richard Hammond , Matthew T. Currie , Eugene A. Fitzgerald
发明人： Anthony J. Lochtefeld , Thomas A. Langdo , Richard Hammond , Matthew T. Currie , Eugene A. Fitzgerald
IPC分类号： H01L21/36
CPC分类号： H01L29/7847 , H01L21/28518 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/165 , H01L29/41783 , H01L29/66242 , H01L29/66628 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/7843 , H01L29/7849 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

3. 发明申请

US20110318893A1 METHODS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURES 有权
标题翻译：形成半导体器件结构的方法
公开(公告)号：US20110318893A1
公开(公告)日：2011-12-29
申请号：US13227077
申请日：2011-09-07
申请人： Anthony J. Lochtefeld , Thomas A. Langdo , Richard Hammond , Matthew T. Currie , Eugene A. Fitzgerald
发明人： Anthony J. Lochtefeld , Thomas A. Langdo , Richard Hammond , Matthew T. Currie , Eugene A. Fitzgerald
IPC分类号： H01L21/336 , H01L21/265 , H01L21/20
CPC分类号： H01L29/7847 , H01L21/28518 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/165 , H01L29/41783 , H01L29/66242 , H01L29/66628 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/7843 , H01L29/7849 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

4. 发明申请

US20110073908A1 III-V Semiconductor Device Structures 有权
标题翻译： III-V半导体器件结构
公开(公告)号：US20110073908A1
公开(公告)日：2011-03-31
申请号：US12907787
申请日：2010-10-19
申请人： Anthony J. Lochtefeld , Thomas A. Langdo , Richard Hammond , Matthew T. Currie , Eugene A. Fitzgerald
发明人： Anthony J. Lochtefeld , Thomas A. Langdo , Richard Hammond , Matthew T. Currie , Eugene A. Fitzgerald
IPC分类号： H01L29/20
CPC分类号： H01L29/7847 , H01L21/28518 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/165 , H01L29/41783 , H01L29/66242 , H01L29/66628 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/7843 , H01L29/7849 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

5. 发明授权

US07682952B2 Method for forming low defect density alloy graded layers and structure containing such layers 有权
标题翻译：用于形成低缺陷密度合金梯度层的方法和包含这种层的结构
公开(公告)号：US07682952B2
公开(公告)日：2010-03-23
申请号：US10999486
申请日：2004-11-30
申请人： David Michael Isaacson , Eugene A. Fitzgerald
发明人： David Michael Isaacson , Eugene A. Fitzgerald
IPC分类号： H01L21/20
CPC分类号： H01L21/02439 , H01L21/0237 , H01L21/02433 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02521 , Y10S438/933 , Y10S438/938
摘要： A structure and method of forming same, comprising a low threading density alloy graded layer, deposited according to a deposition temperature profile in correspondence with increasing alloy composition. In one embodiment, a first substantially relaxed alloy graded layer is deposited while varying a deposition temperature according to a first temperature profile. A second substantially relaxed alloy graded layer is deposited over the first graded layer while varying a deposition temperature according to a second temperature profile. Preferably, the minimum signed rate of change of the second temperature profile is less than the maximum signed rate of change of the first temperature profile.
摘要翻译：根据增加的合金成分，根据沉积温度分布沉积低密度合金渐变层的结构和方法。在一个实施例中，在根据第一温度曲线改变沉积温度的同时沉积第一基本上松弛的合金梯度层。第二基本上松弛的合金梯度层沉积在第一梯度层上，同时根据第二温度曲线改变沉积温度。优选地，第二温度分布的最小有效变化率小于第一温度分布的最大有效变化率。

6. 发明授权

US07674335B2 Method of producing high quality relaxed silicon germanium layers 有权
标题翻译：生产高品质松散硅锗层的方法
公开(公告)号：US07674335B2
公开(公告)日：2010-03-09
申请号：US11371442
申请日：2006-03-09
申请人： Eugene A. Fitzgerald , Richard Westhoff , Matthew T. Currie , Christopher J. Vineis , Thomas A. Langdo
发明人： Eugene A. Fitzgerald , Richard Westhoff , Matthew T. Currie , Christopher J. Vineis , Thomas A. Langdo
IPC分类号： C30B21/02
CPC分类号： C30B29/52 , C23C16/029 , C23C16/22 , C23C16/4401 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262
摘要： A method for minimizing particle generation during deposition of a graded Si1−xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1−xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
摘要翻译：在半导体材料上沉积梯度Si1-xGex层期间最小化颗粒产生的方法包括在包括Si前体和Ge前体的气氛中提供衬底，其中Ge前体的分解温度大于锗烷，并沉积分级的Si1-xGex层，其具有大于约0.15的最终Ge含量和小于约0.3颗粒/ cm 2的颗粒密度。

7. 发明授权

US07566606B2 Methods of fabricating semiconductor devices having strained dual channel layers 有权
标题翻译：制造具有应变双通道层的半导体器件的方法
公开(公告)号：US07566606B2
公开(公告)日：2009-07-28
申请号：US11544245
申请日：2006-10-06
申请人： Matthew T. Currie , Anthony J. Lochtefeld , Christopher W. Leitz , Eugene A. Fitzgerald
发明人： Matthew T. Currie , Anthony J. Lochtefeld , Christopher W. Leitz , Eugene A. Fitzgerald
IPC分类号： H01L21/00
CPC分类号： H01L29/66545 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66628 , H01L29/66636 , H01L29/66651 , H01L29/66916 , H01L29/802 , Y10S438/938
摘要： A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.
摘要翻译：半导体结构包括锗浓度为至少10原子％的应变诱导基底层。半导体结构还包括在应变诱导基底层上的压缩应变层。压缩应变层的锗浓度比应变诱导基底层的锗浓度大至少约30个百分点，并且具有小于其临界厚度的厚度。半导体结构还包括在压缩应变层上的拉伸应变层。拉伸应变层可以由厚度小于其临界厚度的硅形成。一种用于制造半导体结构的方法包括：提供衬底，在衬底上提供压缩应变半导体，在衬底附近沉积拉伸应变半导体，直到拉伸应变半导体的第一区域的厚度大于第二区域的厚度的拉伸应变半导体，在第一区域上形成n沟道器件，并在第二区域上形成p沟道器件。

8. 发明申请

US20080149915A1 Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission 有权
标题翻译：半导体发光结构和提供黄绿色发光的渐变组成基板
公开(公告)号：US20080149915A1
公开(公告)日：2008-06-26
申请号：US11823860
申请日：2007-06-28
申请人： Michael J. Mori , Eugene A. Fitzgerald
发明人： Michael J. Mori , Eugene A. Fitzgerald
IPC分类号： H01L33/00
CPC分类号： H01L33/30 , H01L33/12
摘要： Semiconductor light-emitting structures are shown on engineered substrates having a graded composition. The composition of the substrate may be graded to achieve a lattice constant on which a yellow-green light-emitting semiconductor material may be disposed. In some embodiments, the structure may be substantially free of aluminum.
摘要翻译：半导体发光结构显示在具有渐变组成的工程衬底上。可以对衬底的组成进行分级，以达到可以设置黄绿色发光半导体材料的晶格常数。在一些实施方案中，该结构可以基本上不含铝。

9. 发明授权

US07180648B2 Electro-absorption modulator device and methods for fabricating the same 失效
标题翻译：电吸收式调制装置及其制造方法
公开(公告)号：US07180648B2
公开(公告)日：2007-02-20
申请号：US11151610
申请日：2005-06-13
申请人： Carl Dohrman , Saurabh Gupta , Eugene A. Fitzgerald
发明人： Carl Dohrman , Saurabh Gupta , Eugene A. Fitzgerald
IPC分类号： G02F1/03 , G02F1/01 , H01L31/0328 , H01L31/12 , H01S5/00
CPC分类号： B82Y20/00 , G02F1/017 , G02F2001/0157 , G02F2001/01791
摘要： An electro-absorption light intensity modulator device is provided that comprises a first and a second layer disposed relative to the first layer so as to provide a light-absorbing optical confinement region. The first layer comprises a first insulator layer, and the light-absorbing optical confinement region comprises at least one quantum-confined structure. The at least one quantum-confined structure possesses dimensions such, that upon an application of an electric field in the at least one quantum-confined structure, light absorption is at least partially due to a transition of at least one carrier between a valence state and a conduction state of the at least one quantum-confined structure. A method is also provided for fabricating an electro-absorption light intensity modulator device. The method comprises providing a first insulator layer, disposing a light absorption region over the first insulator layer, and disposing a second insulator layer over the light absorption region, wherein light absorption region comprises at least one quantum-confined structure. The at least one quantum-confined structure possesses dimensions such that, upon an application of an electric field in the at least one quantum-confined structure, light absorption is at least partially due to a transition of at least one carrier between a valence state and a conduction state of the at least one quantum-confined structure.
摘要翻译：提供一种电吸收光强度调制装置，其包括相对于第一层设置的第一和第二层，以便提供光吸收光限制区域。第一层包括第一绝缘体层，并且光吸收光限制区域包括至少一个量子限制结构。所述至少一个量子限制结构具有这样的尺寸，即在施加至少一个量子限制结构中的电场时，光吸收至少部分是由于至少一个载流子在价态和所述至少一个量子限制结构的导电状态。还提供了一种用于制造电吸收光强度调制器装置的方法。该方法包括提供第一绝缘体层，在第一绝缘体层上设置光吸收区域，以及在光吸收区域上设置第二绝缘体层，其中光吸收区域包括至少一个量子限制结构。所述至少一个量子限制结构具有这样的尺寸，使得在至少一个量子限制结构中施加电场时，光吸收至少部分是由于至少一个载体在价态和所述至少一个量子限制结构的导电状态。

10. 发明授权

US07141820B2 Structures with planar strained layers 失效
标题翻译：具有平面应变层的结构
公开(公告)号：US07141820B2
公开(公告)日：2006-11-28
申请号：US10788741
申请日：2004-02-27
申请人： Minjoo L. Lee , Christopher W. Leitz , Eugene A. Fitzgerald
发明人： Minjoo L. Lee , Christopher W. Leitz , Eugene A. Fitzgerald
IPC分类号： H01L29/04
CPC分类号： H01L29/1054 , H01L21/823807 , H01L27/092 , H01L29/78 , H01L29/802
摘要： A structure including a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer may be formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer and/or (ii) having an average height less than 10 nm.
摘要翻译：包括压缩应变半导体层的结构，该压缩应变层具有大于或等于0.25％的应变。可以在压缩应变层上形成拉伸应变半导体层。压缩应变层基本上是平面的，具有表面粗糙度，其特征在于（i）平均波长大于压缩应变层中的载体的平均波长，和/或（ii）平均高度小于10nm。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式