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81. 发明申请

US20060155934A1 System and method for reducing unnecessary cache operations 审中-公开
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US20060155934A1
公开(公告)日：2006-07-13
申请号：US11032875
申请日：2005-01-11
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

82. 发明申请

US20060064518A1 Method and system for managing cache injection in a multiprocessor system 有权
标题翻译：在多处理器系统中管理缓存注入的方法和系统
公开(公告)号：US20060064518A1
公开(公告)日：2006-03-23
申请号：US10948407
申请日：2004-09-23
申请人： Patrick Bohrer , Ahmed Gheith , Peter Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
发明人： Patrick Bohrer , Ahmed Gheith , Peter Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
摘要翻译：用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

83. 发明授权

US06961815B2 Multiple disk data storage system for reducing power consumption 有权
标题翻译：多磁盘数据存储系统，用于降低功耗
公开(公告)号：US06961815B2
公开(公告)日：2005-11-01
申请号：US10313275
申请日：2002-12-05
申请人： Michael David Kistler , Ramakrishnan Rajamony
发明人： Michael David Kistler , Ramakrishnan Rajamony
IPC分类号： G06F1/32 , G06F11/20 , G06F12/00
CPC分类号： G06F1/3268 , G06F1/3203 , G06F3/0625 , G06F3/0634 , G06F3/0643 , G06F3/0689 , G06F11/1076 , G06F11/2069 , G06F2211/1059 , G06F2211/1061 , Y02D10/154 , Y02D50/20
摘要： A disk controller connected to a set of disks in a data storage system is configured to mirror a first class of data on multiple disks while storing a second class of data without mirroring. The controller maintains at least one of the disks containing the first class of data in an operational state while maintaining at least one of the remaining disks in a low power state. The first class of data may contain popular files while the second class of data contains unpopular files. The first data class may be mirrored on each of the disks. The data in the second class may be stored with parity where the parity information is maintained on a single disk. The operational disk may be changed following access to data from the second class of data that is stored on one of the low power state disks.
摘要翻译：连接到数据存储系统中的一组磁盘的磁盘控制器被配置为在多个磁盘上镜像第一类数据，同时存储第二类数据而不进行镜像。控制器将包含第一类数据的至少一个盘维持在操作状态，同时将至少一个其余盘保持在低功率状态。第一类数据可能包含受欢迎的文件，而第二类数据包含不受欢迎的文件。可以在每个磁盘上镜像第一个数据类。第二类中的数据可以以奇偶校验存储，其中奇偶校验信息被保持在单个盘上。在从存储在低功率状态磁盘之一的第二类数据中访问数据之后，可以改变操作盘。

84. 发明授权

US06925529B2 Data storage on a multi-tiered disk system 失效
标题翻译：数据存储在多层磁盘系统上
公开(公告)号：US06925529B2
公开(公告)日：2005-08-02
申请号：US09903721
申请日：2001-07-12
申请人： Patrick J. Bohrer , Elmootazbellah N. Elnozahy , Charles R. Lefurgy , Ramakrishnan Rajamony , Bruce A. Smith
发明人： Patrick J. Bohrer , Elmootazbellah N. Elnozahy , Charles R. Lefurgy , Ramakrishnan Rajamony , Bruce A. Smith
IPC分类号： G06F1/32 , G06F3/06 , G06F12/00
CPC分类号： G06F3/0634 , G06F1/3221 , G06F1/3268 , G06F3/0625 , G06F3/0689 , Y02D10/154
摘要： A method and a computer usable medium including a program for operating disks having units, comprising: providing a first tier of at least one disk, the first tier storing at least one popular unit, providing a second tier of at least one disk, the second tier storing at least one unpopular unit, powering on at least one first tier disk, powering down the second tier, determining whether a request for a unit requires processing on the first tier or second tier, accessing the requested unit if the requested unit requires processing on the first tier, and powering on a second tier disk to copy the requested unit from the second tier disk to a first tier disk, if the requested unit is stored on the second tier.
摘要翻译：一种包括用于操作具有单元的盘的程序的方法和计算机可用介质，包括：提供至少一个盘的第一层，所述第一层存储至少一个流行单元，提供至少一个盘的第二层，所述第二层存储至少一个不受欢迎的单元，为至少一个第一层磁盘供电;关闭第二层的电源;确定对单元的请求是否需要对第一层或第二层进行处理，如果请求的单元需要处理，则访问所请求的单元如果所请求的单元存储在第二层上，则启动第二层磁盘以将请求的单元从第二层磁盘复制到第一层磁盘。

85. 发明申请

US20050132068A1 Estimating bandwidth of client-ISP link 有权
标题翻译：估计客户端 - ISP链路的带宽
公开(公告)号：US20050132068A1
公开(公告)日：2005-06-16
申请号：US10734771
申请日：2003-12-12
申请人： Ramakrishnan Rajamony
发明人： Ramakrishnan Rajamony
IPC分类号： G06F15/16 , G06F15/173 , H04L12/24 , H04L12/26 , H04L29/12
CPC分类号： H04L61/304 , H04L29/12594 , H04L41/0896 , H04L43/00 , H04L43/0882 , H04L43/50 , H04L61/30
摘要： A method, program, and server for estimating the bandwidth of a network connection between a client and a server includes requesting the server to serve first and second objects back-to-back to the client. The first and second objects are sent to the client. The client determines the time interval between delivery of the first and second objects. The time interval is used, in conjunction with information about the size of the second object, to estimate the bandwidth. The requests for the first and second objects preferably identify the first and second objects with URL's that are unique on the network to prevent the request from being serviced by a file cache. The first and second objects may be transmitted to the client from a content distribution network server that is architecturally close to the client's ISP to improve the reliability of the bandwidth estimation.
摘要翻译：用于估计客户端和服务器之间的网络连接的带宽的方法，程序和服务器包括请求服务器将第一和第二对象反向服务于客户端。第一个和第二个对象被发送到客户端。客户端确定第一个和第二个对象的传递之间的时间间隔。使用时间间隔结合关于第二对象的大小的信息来估计带宽。对第一和第二对象的请求优选地识别具有在网络上唯一的URL的第一和第二对象，以防止该请求由文件高速缓存服务。第一和第二对象可以从架构上靠近客户端的ISP的内容分发网络服务器发送到客户端，以提高带宽估计的可靠性。

86. 发明授权

US06711650B1 Method and apparatus for accelerating input/output processing using cache injections 失效
标题翻译：用于使用高速缓存注入加速输入/输出处理的方法和装置
公开(公告)号：US06711650B1
公开(公告)日：2004-03-23
申请号：US10289817
申请日：2002-11-07
申请人： Patrick Joseph Bohrer , Ramakrishnan Rajamony , Hazim Shafi
发明人： Patrick Joseph Bohrer , Ramakrishnan Rajamony , Hazim Shafi
IPC分类号： G06F1202
CPC分类号： G06F12/0835
摘要： A method for accelerating input/output operations within a data processing system is disclosed. Initially, a determination is initially made in a cache controller as to whether or not a bus operation is a data transfer from a first memory to a second memory without intervening communications through a processor, such as a direct memory access (DMA) transfer. If the bus operation is such data transfer, a determination is made in a cache memory as to whether or not the cache memory includes a copy of data from the data transfer. If the cache memory does not include a copy of data from the data transfer, a cache line is allocated within the cache memory to store a copy of data from the data transfer.
摘要翻译：公开了一种用于加速数据处理系统内的输入/输出操作的方法。最初，在高速缓存控制器中首先确定总线操作是否是从第一存储器到第二存储器的数据传输，而不需要通过诸如直接存储器访问（DMA）传送的处理器进行通信。如果总线操作是这种数据传输，则在高速缓冲存储器中确定高速缓冲存储器是否包括来自数据传输的数据的副本。如果高速缓冲存储器不包括来自数据传输的数据的副本，则在高速缓冲存储器内分配高速缓存线以存储来自数据传输的数据副本。

87. 发明授权

US06473819B1 Scalable interruptible queue locks for shared-memory multiprocessor 有权
标题翻译：可扩展的可中断队列锁为共享内存多处理器
公开(公告)号：US06473819B1
公开(公告)日：2002-10-29
申请号：US09465297
申请日：1999-12-17
申请人： Benedict Joseph Jackson , Paul Edward McKenney , Ramakrishnan Rajamony , Ronald Lynn Rockhold
发明人： Benedict Joseph Jackson , Paul Edward McKenney , Ramakrishnan Rajamony , Ronald Lynn Rockhold
IPC分类号： G06F1200
CPC分类号： G06F9/52
摘要： A method for a computation agent to acquire a queue lock in a multiprocessor system that prevents deadlock between the computation agent and external interrupts. The method provides for the computation agent to join a queue to acquire a lock. Next, upon receiving ownership of the lock, the computation agent raises its priority level to a higher second priority level. In response to a receipt of an external interrupt having a higher priority level occurring before the computation agent has raised its priority level to the second higher priority level, the computation agent relinquishes ownership of the lock. Subsequent to raising its priority level to the second higher priority level, the computation agent determines if it still has ownership of the lock. If the computation agent determines that it has not acquired possession of the lock after raising its priority level, the computation agent rejoins the queue to reacquire the lock. In one embodiment of the present invention, the computation agent's priority level is restored to its original, i.e., first priority level, when it rejoins the queue to reacquire the lock.
摘要翻译：一种用于计算代理获取多处理器系统中的队列锁的方法，其防止计算代理和外部中断之间的死锁。该方法提供计算代理加入队列以获取锁。接下来，在获得锁的所有权时，计算代理将其优先级提高到更高的第二优先级。响应于在计算代理已经将其优先级提高到第二较高优先级之前发生具有较高优先级的外部中断的接收，计算代理放弃对锁的所有权。在将其优先级提高到第二高优先级之后，计算代理确定它是否仍具有锁的所有权。如果计算代理确定在提升其优先级后尚未获得该锁的拥有权，则计算代理重新加入队列以重新获取该锁。在本发明的一个实施例中，当它重新加入队列以重新获取锁时，计算代理的优先级被恢复到其原始的，即第一优先级。

88. 发明授权

US06421775B1 Interconnected processing nodes configurable as at least one non-uniform memory access (NUMA) data processing system 有权
标题翻译：互连处理节点可配置为至少一个非均匀存储器访问（NUMA）数据处理系统
公开(公告)号：US06421775B1
公开(公告)日：2002-07-16
申请号：US09335301
申请日：1999-06-17
申请人： Bishop Chapman Brock , David Brian Glasco , James Lyle Peterson , Ramakrishnan Rajamony , Ronald Lynn Rockhold
发明人： Bishop Chapman Brock , David Brian Glasco , James Lyle Peterson , Ramakrishnan Rajamony , Ronald Lynn Rockhold
IPC分类号： G06F15177
CPC分类号： G06F15/177
摘要： A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.
摘要翻译：数据处理系统包括多个处理节点，每个处理节点包含至少一个处理器和数据存储器。多个处理节点通过系统互连耦合在一起。数据处理系统还包括驻留在多个处理节点中的至少一个处理节点内的数据存储器中的配置实用程序。配置实用程序通过经由系统互连的通信将多个处理节点选择性地配置为单个非均匀存储器访问（NUMA）系统或多个独立的数据处理系统。

89. 发明授权

US09152569B2 Non-uniform cache architecture (NUCA) 有权
标题翻译：非均匀缓存架构（NUCA）
公开(公告)号：US09152569B2
公开(公告)日：2015-10-06
申请号：US12264682
申请日：2008-11-04
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Xiaoxia Wu , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Xiaoxia Wu , Lixin Zhang
IPC分类号： G06F12/02 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0846 , G06F12/0848 , G06F12/123 , G06F2212/225 , G06F2212/271
摘要： In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.
摘要翻译：在一个实施例中，高速缓存存储器包括高速缓存阵列，其包括用于缓存高速缓存行数据的多个条目，其中多个条目分布在以第一存储器技术实现的第一区域和在第二存储器技术中实现的第二区域之间。高速缓冲存储器还包括高速缓存阵列的内容的高速缓存目录和控制高速缓冲存储器的操作的高速缓存控制器。

90. 发明授权

US08893148B2 Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks 有权
标题翻译：执行设置操作以在处理器执行消息传递接口任务时接收不同数量的数据
公开(公告)号：US08893148B2
公开(公告)日：2014-11-18
申请号：US13524585
申请日：2012-06-15
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46 , G06F9/50 , G06F9/52
CPC分类号： G06F9/522 , G06F9/5083
摘要： A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.
摘要翻译：提供了一种系统和方法，用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数量的数据的建立操作。提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。

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