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81. 发明申请

US20110173343A1 ZONE ROUTING IN A TORUS NETWORK 失效
标题翻译：多功能网络中的区域路由
公开(公告)号：US20110173343A1
公开(公告)日：2011-07-14
申请号：US12684184
申请日：2010-01-08
申请人： Dong Chen , Philip Heidelberger , Sameer Kumar
发明人： Dong Chen , Philip Heidelberger , Sameer Kumar
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A system for routing data in a network comprising a network logic device at a sending node for determining a path between the sending node and a receiving node, wherein the network logic device sets one or more selection bits and one or more hint bits within the data packet, a control register for storing one or more masks, wherein the network logic device uses the one or more selection bits to select a mask from the control register and the network logic device applies the selected mask to the hint bits to restrict routing of the data packet to one or more routing directions for the data packet within the network and selects one of the restricted routing directions from the one or more routing directions and sends the data packet along a link in the selected routing direction toward the receiving node.
摘要翻译：一种用于在网络中路由数据的系统，包括在发送节点处的网络逻辑设备，用于确定发送节点和接收节点之间的路径，其中网络逻辑设备设置数据内的一个或多个选择位和一个或多个提示位分组，用于存储一个或多个掩码的控制寄存器，其中所述网络逻辑设备使用所述一个或多个选择位从所述控制寄存器中选择掩码，并且所述网络逻辑设备将所选择的掩码应用于所述提示位以限制数据分组发送到网络内的数据分组的一个或多个路由方向，并且从一个或多个路由选择中选择一个受限制的路由方向，并沿所选路由方向的链路向接收节点发送数据分组。

82. 发明授权

US08032892B2 Message passing with a limited number of DMA byte counters 失效
标题翻译：消息传递有限数量的DMA字节计数器
公开(公告)号：US08032892B2
公开(公告)日：2011-10-04
申请号：US11768813
申请日：2007-06-26
申请人： Michael Blocksome , Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
发明人： Michael Blocksome , Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
IPC分类号： G06F9/44 , G06F9/46 , G06F13/00 , G06F15/167
CPC分类号： G06F15/17356 , G06F9/546
摘要： A method for passing messages in a parallel computer system constructed as a plurality of compute nodes interconnected as a network where each compute node includes a DMA engine but includes only a limited number of byte counters for tracking a number of bytes that are sent or received by the DMA engine, where the byte counters may be used in shared counter or exclusive counter modes of operation. The method includes using rendezvous protocol, a source compute node deterministically sending a request to send (RTS) message with a single RTS descriptor using an exclusive injection counter to track both the RTS message and message data to be sent in association with the RTS message, to a destination compute node such that the RTS descriptor indicates to the destination compute node that the message data will be adaptively routed to the destination node. Using one DMA FIFO at the source compute node, the RTS descriptors are maintained for rendezvous messages destined for the destination compute node to ensure proper message data ordering thereat. Using a reception counter at a DMA engine, the destination compute node tracks reception of the RTS and associated message data and sends a clear to send (CTS) message to the source node in a rendezvous protocol form of a remote get to accept the RTS message and message data and processing the remote get (CTS) by the source compute node DMA engine to provide the message data to be sent.
摘要翻译：一种在并行计算机系统中传送消息的方法，该并行计算机系统被构造为作为网络互连的多个计算节点，其中每个计算节点包括DMA引擎，但是仅包括有限数量的字节计数器，用于跟踪由 DMA引擎，其中可以在共享计数器或专用计数器操作模式中使用字节计数器。该方法包括使用会合协议，源计算节点使用专用注入计数器确定性地发送具有单个RTS描述符的请求（RTS）消息以跟踪要与RTS消息相关联地发送的RTS消息和消息数据，到目的地计算节点，使得RTS描述符向目标计算节点指示消息数据将自适应地路由到目的地节点。在源计算节点使用一个DMA FIFO，将为发往目的地计算节点的会合消息保留RTS描述符，以确保正确的消息数据顺序。在DMA引擎上使用接收计数器，目的地计算节点跟踪RTS和相关联的消息数据的接收，并以远程获取的会合协议形式向源节点发送明确发送（CTS）消息以接受RTS消息和消息数据，并由源计算节点DMA引擎处理远程获取（CTS）以提供要发送的消息数据。

83. 发明申请

US20080307121A1 Direct Memory Access Transfer Completion Notification 失效
标题翻译：直接内存访问传输完成通知
公开(公告)号：US20080307121A1
公开(公告)日：2008-12-11
申请号：US11758167
申请日：2007-06-05
申请人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.
摘要翻译：提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

84. 发明授权

US08359404B2 Zone routing in a torus network 失效
标题翻译：环网中的区域路由
公开(公告)号：US08359404B2
公开(公告)日：2013-01-22
申请号：US12684184
申请日：2010-01-08
申请人： Dong Chen , Philip Heidelberger , Sameer Kumar
发明人： Dong Chen , Philip Heidelberger , Sameer Kumar
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A system for routing data in a network comprising a network logic device at a sending node for determining a path between the sending node and a receiving node, wherein the network logic device sets one or more selection bits and one or more hint bits within the data packet, a control register for storing one or more masks, wherein the network logic device uses the one or more selection bits to select a mask from the control register and the network logic device applies the selected mask to the hint bits to restrict routing of the data packet to one or more routing directions for the data packet within the network and selects one of the restricted routing directions from the one or more routing directions and sends the data packet along a link in the selected routing direction toward the receiving node.
摘要翻译：一种用于在网络中路由数据的系统，包括在发送节点处的网络逻辑设备，用于确定发送节点和接收节点之间的路径，其中网络逻辑设备设置数据内的一个或多个选择位和一个或多个提示位分组，用于存储一个或多个掩码的控制寄存器，其中所述网络逻辑设备使用所述一个或多个选择位从所述控制寄存器中选择掩码，并且所述网络逻辑设备将所选择的掩码应用于所述提示位以限制数据分组发送到网络内的数据分组的一个或多个路由方向，并且从一个或多个路由选择中选择一个受限制的路由方向，并沿所选路由方向的链路向接收节点发送数据分组。

85. 发明授权

US07765337B2 Direct memory access transfer completion notification 失效
标题翻译：直接内存访问传输完成通知
公开(公告)号：US07765337B2
公开(公告)日：2010-07-27
申请号：US11758167
申请日：2007-06-05
申请人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28 , G06F3/00 , G06F13/00
CPC分类号： G06F13/28
摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.
摘要翻译：提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

86. 发明申请

US20090007141A1 MESSAGE PASSING WITH A LIMITED NUMBER OF DMA BYTE COUNTERS 失效
标题翻译：消息传递与有限数量的DMA字节计数器
公开(公告)号：US20090007141A1
公开(公告)日：2009-01-01
申请号：US11768813
申请日：2007-06-26
申请人： Michael Blocksome , Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
发明人： Michael Blocksome , Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
IPC分类号： G06F9/44
CPC分类号： G06F15/17356 , G06F9/546
摘要： A method for passing messages in a parallel computer system constructed as a plurality of compute nodes interconnected as a network where each compute node includes a DMA engine but includes only a limited number of byte counters for tracking a number of bytes that are sent or received by the DMA engine, where the byte counters may be used in shared counter or exclusive counter modes of operation. The method includes using rendezvous protocol, a source compute node deterministically sending a request to send (RTS) message with a single RTS descriptor using an exclusive injection counter to track both the RTS message and message data to be sent in association with the RTS message, to a destination compute node such that the RTS descriptor indicates to the destination compute node that the message data will be adaptively routed to the destination node. Using one DMA FIFO at the source compute node, the RTS descriptors are maintained for rendezvous messages destined for the destination compute node to ensure proper message data ordering thereat. Using a reception counter at a DMA engine, the destination compute node tracks reception of the RTS and associated message data and sends a clear to send (CTS) message to the source node in a rendezvous protocol form of a remote get to accept the RTS message and message data and processing the remote get (CTS) by the source compute node DMA engine to provide the message data to be sent.
摘要翻译：一种在并行计算机系统中传送消息的方法，该并行计算机系统被构造为作为网络互连的多个计算节点，其中每个计算节点包括DMA引擎，但是仅包括有限数量的字节计数器，用于跟踪由 DMA引擎，其中可以在共享计数器或专用计数器操作模式中使用字节计数器。该方法包括使用会合协议，源计算节点使用专用注入计数器确定性地发送具有单个RTS描述符的请求（RTS）消息以跟踪要与RTS消息相关联地发送的RTS消息和消息数据，到目的地计算节点，使得RTS描述符向目标计算节点指示消息数据将自适应地路由到目的地节点。在源计算节点使用一个DMA FIFO，将为发往目的地计算节点的会合消息保留RTS描述符，以确保正确的消息数据顺序。在DMA引擎上使用接收计数器，目的地计算节点跟踪RTS和相关联的消息数据的接收，并以远程获取的会合协议形式向源节点发送明确发送（CTS）消息以接受RTS消息和消息数据，并由源计算节点DMA引擎处理远程获取（CTS）以提供要发送的消息数据。

87. 发明申请

US20070055825A1 Managing coherence via put/get windows 失效
标题翻译：通过put / get窗口管理一致性
公开(公告)号：US20070055825A1
公开(公告)日：2007-03-08
申请号：US10468995
申请日：2002-02-25
申请人： Matthias Blumrich , Dong Chan , Paul Coteus , Alan Gata , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias Blumrich , Dong Chan , Paul Coteus , Alan Gata , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F13/28
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

88. 发明授权

US08407376B2 Recording a communication pattern and replaying messages in a parallel computing system 失效
标题翻译：记录通信模式并在并行计算系统中重播消息
公开(公告)号：US08407376B2
公开(公告)日：2013-03-26
申请号：US12500715
申请日：2009-07-10
申请人： Philip Heidelberger , Sameer Kumar
发明人： Philip Heidelberger , Sameer Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A parallel computer system includes a plurality of compute nodes. Each of the compute nodes includes at least one processor, at least one memory, and a direct memory address engine coupled to the at least one processor and the at least one memory. The system also includes a network interconnecting the plurality of compute nodes. The network operates a global message-passing application for performing communications across the network. Local instances of the global message-passing application operate at each of the compute nodes to carry out local processing operations independent of processing operations carried out at another one of the compute nodes. The direct memory address engines are configured to interact with the local instances of the global message-passing application via injection FIFO metadata describing an injection FIFO in a corresponding one of the memories. The local instances of the global message passing application are configured to record, in the injection FIFO in the corresponding one of the memories, message descriptors associated with messages of an arbitrary communication pattern in an iteration of an executing application program. The local instances of the global message passing application are configured to replay the message descriptors during a subsequent iteration of the executing application program.
摘要翻译：并行计算机系统包括多个计算节点。每个计算节点包括耦合到至少一个处理器和至少一个存储器的至少一个处理器，至少一个存储器和直接存储器地址引擎。该系统还包括互连多个计算节点的网络。该网络运行全球消息传递应用程序，用于跨网络执行通信。全局消息传递应用的本地实例在每个计算节点处操作，以独立于在另一个计算节点处执行的处理操作来执行本地处理操作。直接存储器地址引擎被配置为通过描述在对应的一个存储器中的注入FIFO的注入FIFO元数据与全局消息传递应用的本地实例进行交互。全局消息传递应用程序的本地实例被配置为在执行的应用程序的迭代中在对应的一个存储器中的注入FIFO中记录与任意通信模式的消息相关联的消息描述符。全局消息传递应用程序的本地实例被配置为在执行的应用程序的后续迭代期间重播消息描述符。

89. 发明申请

US20110010471A1 Recording A Communication Pattern and Replaying Messages in a Parallel Computing System 失效
标题翻译：在并行计算系统中记录通信模式和回放消息
公开(公告)号：US20110010471A1
公开(公告)日：2011-01-13
申请号：US12500715
申请日：2009-07-10
申请人： Philip Heidelberger , Sameer Kumar
发明人： Philip Heidelberger , Sameer Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A parallel computer system includes a plurality of compute nodes. Each of the compute nodes includes at least one processor, at least one memory, and a direct memory address engine coupled to the at least one processor and the at least one memory. The system also includes a network interconnecting the plurality of compute nodes. The network operates a global message-passing application for performing communications across the network. Local instances of the global message-passing application operate at each of the compute nodes to carry out local processing operations independent of processing operations carried out at another one of the compute nodes. The direct memory address engines are configured to interact with the local instances of the global message-passing application via injection FIFO metadata describing an injection FIFO in a corresponding one of the memories. The local instances of the global message passing application are configured to record, in the injection FIFO in the corresponding one of the memories, message descriptors associated with messages of an arbitrary communication pattern in an iteration of an executing application program. The local instances of the global message passing application are configured to replay the message descriptors during a subsequent iteration of the executing application program.
摘要翻译：并行计算机系统包括多个计算节点。每个计算节点包括耦合到至少一个处理器和至少一个存储器的至少一个处理器，至少一个存储器和直接存储器地址引擎。该系统还包括互连多个计算节点的网络。该网络运行全球消息传递应用程序，用于跨网络执行通信。全局消息传递应用的本地实例在每个计算节点处操作，以独立于在另一个计算节点处执行的处理操作来执行本地处理操作。直接存储器地址引擎被配置为通过描述在对应的一个存储器中的注入FIFO的注入FIFO元数据与全局消息传递应用的本地实例进行交互。全局消息传递应用程序的本地实例被配置为在执行的应用程序的迭代中在对应的一个存储器中的注入FIFO中记录与任意通信模式的消息相关联的消息描述符。全局消息传递应用程序的本地实例被配置为在执行的应用程序的后续迭代期间重播消息描述符。

90. 发明申请

US20100268852A1 Replenishing Data Descriptors in a DMA Injection FIFO Buffer 失效
标题翻译：在DMA注入FIFO缓冲区中补充数据描述符
公开(公告)号：US20100268852A1
公开(公告)日：2010-10-21
申请号：US11755501
申请日：2007-05-30
申请人： Charles J Archer , Michael A. Blocksome , Bob R. Cernohous , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
发明人： Charles J Archer , Michael A. Blocksome , Bob R. Cernohous , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Methods, apparatus, and products are disclosed for replenishing data descriptors in a Direct Memory Access (‘DMA’) injection first-in-first-out (‘FIFO’) buffer that include: determining, by a messaging module on an origin compute node, whether a number of data descriptors in a DMA injection FIFO buffer exceeds a predetermined threshold, each data descriptor specifying an application message for transmission to a target compute node; queuing, by the messaging module, a plurality of new data descriptors in a pending descriptor queue if the number of the data descriptors in the DMA injection FIFO buffer exceeds the predetermined threshold; establishing, by the messaging module, interrupt criteria that specify when to replenish the injection FIFO buffer with the plurality of new data descriptors in the pending descriptor queue; and injecting, by the messaging module, the plurality of new data descriptors into the injection FIFO buffer in dependence upon the interrupt criteria.
摘要翻译：公开了用于在直接存储器访问（“DMA”）注入先进先出（'FIFO'）缓冲器中补充数据描述符的方法，装置和产品，其包括：由原始计算节点无论DMA注入FIFO缓冲器中的多个数据描述符是否超过预定阈值，每个数据描述符指定用于传输到目标计算节点的应用消息; 如果DMA注入FIFO缓冲器中的数据描述符的数量超过预定阈值，则由消息接发模块排队等待描述符队列中的多个新数据描述符; 由所述消息传递模块建立中断标准，所述中断标准指定何时用所述待处理描述符队列中的所述多个新数据描述符补充所述注入FIFO缓冲器; 以及根据所述中断标准，由所述消息收发模块将所述多个新数据描述符注入到所述注入FIFO缓冲器中。

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