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81. 发明授权

US5852497A Method and apparatus for detecting edges under an opaque layer 失效
标题翻译：用于检测不透明层下方边缘的方法和装置
公开(公告)号：US5852497A
公开(公告)日：1998-12-22
申请号：US919200
申请日：1997-08-28
申请人： Dipankar Pramanik , Kouros Ghandehari , Satyendra S. Sethi , Daniel C. Baker
发明人： Dipankar Pramanik , Kouros Ghandehari , Satyendra S. Sethi , Daniel C. Baker
IPC分类号： G03F9/00 , G01B11/27
CPC分类号： G03F9/70
摘要： The present invention is directed to a method and apparatus for detecting edges through one or more opaque, planarized layers of material. Exemplary embodiments can take full advantage of decreased size geometries associated, such as 0.25 micron technologies, without suffering inaccuracies due to wafer misalignment during processing (e.g., during a photolithographic process). The invention is applicable to any process where an edge is to be detected through a planarized layer which is opaque to visible light. In an exemplary embodiment, an edge of an alignment mark can be detected using an energy source having a wavelength and angle of incidence specifically selected with respect to the optical characteristics and thickness of particular material layers being processed. According to exemplary embodiments, the wavelength of the energy source selected, such as an infrared light source, can be determined on the basis of an absorption coefficient of the planarized opaque material through which edge detection is to be performed (e.g., through a planarized polysilicon layer), and on the basis of a predetermined thickness with which the planarized polysilicon layer is formed.
摘要翻译：本发明涉及一种用于通过一个或多个不透明的平坦化材料层检测边缘的方法和装置。示例性实施例可以充分利用相关联的尺寸减小的尺寸（例如0.25微米技术），而不会由于处理期间的晶片未对准（例如，在光刻工艺期间）而导致不准确。本发明可应用于通过对可见光不透明的平坦化层来检测边缘的任何工艺。在示例性实施例中，可以使用具有相对于被处理的特定材料层的光学特性和厚度特别选择的入射波长和入射角的能量源来检测对准标记的边缘。根据示例性实施例，可以基于要执行边缘检测的平面化不透明材料的吸收系数（例如，通过平坦化多晶硅）来确定所选择的能量源的波长，例如红外光源层），并且基于形成平坦化的多晶硅层的预定厚度。

82. 发明授权

US5811346A Silicon corner rounding in shallow trench isolation process 失效
标题翻译：硅角圆化在浅沟槽隔离过程中
公开(公告)号：US5811346A
公开(公告)日：1998-09-22
申请号：US837161
申请日：1997-04-14
申请人： Harlan Sur , Olivier Laparra , Dipankar Pramanik
发明人： Harlan Sur , Olivier Laparra , Dipankar Pramanik
IPC分类号： H01L21/76 , H01L21/762 , H07L21/76
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A semiconductor device isolating structure and method for forming such a structure. In one embodiment, an opening is formed through a mask layer overlying a semiconductor substrate. A trench of a desired depth is then etched into the semiconductor substrate at the area of the semiconductor substrate underlying the opening in the mask layer. The trench is then filled with a dielectric material. After an oxide planarizing process, the present invention exposes the dielectric-filled trench to an oxidizing environment. By filling the trench with dielectric material prior to the oxidization step, the present invention selectively oxidizes the semiconductor substrate at corners formed by the intersection of the sidewalls of the trench and the top surface of the semiconductor substrate. In so doing, the present invention forms smoothly rounded semiconductor substrate corners under the mask layer. Thus, the present invention eliminates the sharp upper corners associated with prior art shallow trench isolation methods.
摘要翻译：一种用于形成这种结构的半导体器件隔离结构和方法。在一个实施例中，通过覆盖半导体衬底的掩模层形成开口。然后在掩模层中的开口下方的半导体衬底的区域处将期望深度的沟槽蚀刻到半导体衬底中。然后用电介质材料填充沟槽。在氧化物平面化处理之后，本发明将电介质填充的沟槽暴露于氧化环境。通过在氧化步骤之前用电介质材料填充沟槽，本发明在由沟槽的侧壁和半导体衬底的顶表面的相交处形成的拐角处选择性地氧化半导体衬底。这样做，本发明在掩模层下形成平滑的圆形半导体衬底拐角。因此，本发明消除了与现有技术的浅沟槽隔离方法相关联的尖锐的上角。

83. 发明授权

US5522957A Method for leak detection in etching chambers 失效
标题翻译：腐蚀室泄漏检测方法
公开(公告)号：US5522957A
公开(公告)日：1996-06-04
申请号：US171491
申请日：1993-12-22
申请人： Milind Weling , Calvin T. Gabriel , Vivek Jain , Dipankar Pramanik
发明人： Milind Weling , Calvin T. Gabriel , Vivek Jain , Dipankar Pramanik
IPC分类号： H01J37/32 , H01L21/306
CPC分类号： H01J37/3244 , H01J37/32935 , Y10S148/162
摘要： A method and apparatus for detecting the presence of gaseous impurities, notably oxygen, in a gas mixture that flows over an IC wafer in an etcher during the etching process. The method is based upon the discovery that the ratio of the etch rate of spin-on-glass material to the etch rate of other materials, such as plasma-enhanced chemical vapor deposition (PECVD oxide) materials, varies in a predictable manner with the amount of oxygen contaminating the gas mixture. The standard ratio, in the absence of oxygen, is determined for a given set of processing conditions by first etching an SOG wafer, then etching a PECVD oxide material wafer, measuring the amount of material etched in each case, and from that calculating the respective etch rates, and finally taking the ratio of the two calculated etch rates. This standard ratio is used as the benchmark for future tests. When a production run is to be conducted on a new material, the above procedure is repeated when the equipment is otherwise ready for the run, and the new calculated etch rate ratio is compared with the standard ratio. If they are substantially equal, this indicates a lack of oxygen contamination. If the ratio has changed, and other processing conditions have been taken into account (such as RF power and temperature), this indicates the presence of impurities in the gas mixture, and hence probably a leak in the system, or contamination of the gas source itself. In IC manufacturing, the production run is then typically stopped to correct the problem. Calibration data can be generated in advance to determine by how much to adjust the etching time, given a particular measured ratio that is not the same as the standard ratio. The system may be automatically controlled by a computer that calculates the corrected etching time based upon the measured ratio of the respective etch rates of SOG and the PECVD oxide material.
摘要翻译：一种用于在蚀刻过程期间在蚀刻器中流过IC晶片的气体混合物中检测气态杂质（特别是氧）的存在的方法和装置。该方法基于以下发现：旋涂玻璃材料的蚀刻速率与其它材料（诸如等离子体增强化学气相沉积（PECVD氧化物）材料）的蚀刻速率的比率以可预测的方式以氧气混合物的污染量。在不存在氧的情况下，通过首先蚀刻SOG晶片，然后蚀刻PECVD氧化物材料晶片，测量在每种情况下蚀刻的材料的量，并从计算相应的蚀刻速率，最后得到两个计算的蚀刻速率的比值。该标准比例被用作未来测试的基准。当对新材料进行生产运行时，当设备准备运行时，重复上述步骤，并将新计算的蚀刻速率比与标准比率进行比较。如果它们基本相同，则这表明缺乏氧气污染。如果比例发生变化，并考虑了其他加工条件（如RF功率和温度），则表明气体混合物中存在杂质，因此可能是系统泄漏或气体源的污染本身。在IC制造中，通常停止生产运行以纠正问题。可以预先产生校准数据，以确定调整蚀刻时间的程度，给定与标准比率不同的特定测量比。该系统可以由计算机自动控制，该计算机基于SOG和PECVD氧化物材料的相应蚀刻速率的测量比来计算校正的蚀刻时间。

84. 发明授权

US5492865A Method of making structure for suppression of field inversion caused by charge build-up in the dielectric 失效
标题翻译：制造电介质中电荷积聚引起的场反转抑制结构的方法
公开(公告)号：US5492865A
公开(公告)日：1996-02-20
申请号：US314425
申请日：1994-09-28
申请人： Subhash R. Nariani , Vivek Jain , Dipankar Pramanik , Kuang-Yeh Chang
发明人： Subhash R. Nariani , Vivek Jain , Dipankar Pramanik , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/314 , H01L21/316 , H01L23/29 , H01L23/532 , H01L27/115 , H01L21/44 , H01L21/48
CPC分类号： H01L23/291 , H01L21/314 , H01L23/298 , H01L23/5329 , H01L27/115 , H01L2924/0002 , Y10S438/91 , Y10S438/958
摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
摘要翻译：本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

85. 发明授权

US5290727A Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors 失效
标题翻译：用于抑制EEPROM / EPROMS中的电荷损耗的方法和SRAM负载电阻的不稳定性
公开(公告)号：US5290727A
公开(公告)日：1994-03-01
申请号：US860370
申请日：1992-03-30
申请人： Vivek Jain , Dipankar Pramanik , Subhash Nariani
发明人： Vivek Jain , Dipankar Pramanik , Subhash Nariani
IPC分类号： H01L21/8247 , H01L21/314 , H01L21/316 , H01L21/8244 , H01L23/29 , H01L23/532 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/70
CPC分类号： H01L27/11 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/314 , H01L21/31604 , H01L21/31612 , H01L23/291 , H01L23/298 , H01L23/5329 , H01L27/115 , H01L2924/0002
摘要： Suppression of charge loss and hot carrier degradation in EEPROMs and EPROMs, and of instability in the polysilicon pull-up resistors associated with SRAMs is achieved by the inclusion of at least one layer of silicon-enriched oxide in the MOS structure. In such MOS structures, the silicon-enriched oxide layer may be disposed immediately beneath the interlayer dielectric layer, or immediately beneath the inter-metal oxide layer, or immediately beneath the passivation layer, or in any combination of these locations. Each silicon-enriched oxide layer preferably contains at least about 10.sup.17 per cm.sup.3 dangling bonds.
摘要翻译：通过在MOS结构中包含至少一层富含氧化物的氧化物来实现EEPROM和EPROM中的电荷损耗和热载流子劣化的抑制以及与SRAM相关的多晶硅上拉电阻的不稳定性。在这种MOS结构中，富硅氧化物层可以紧邻在层间电介质层的下方，或紧邻金属间氧化物层的正下方，或紧邻钝化层的下方，或者以这些位置的任意组合设置。每个富硅氧化物层优选含有至少约1017个/ cm3悬挂键。

86. 发明授权

US08854067B2 Circular transmission line methods compatible with combinatorial processing of semiconductors 有权
标题翻译：圆形传输线方法兼容半导体的组合处理
公开(公告)号：US08854067B2
公开(公告)日：2014-10-07
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08 , G01R31/28
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

87. 发明授权

US08762924B2 Analysis of stress impact on transistor performance 有权
标题翻译：应力对晶体管性能的影响分析
公开(公告)号：US08762924B2
公开(公告)日：2014-06-24
申请号：US12510188
申请日：2009-07-27
申请人： Victor Moroz , Dipankar Pramanik
发明人： Victor Moroz , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/5081
摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.
摘要翻译：粗略地描述了一种用于近似集成电路布局中的沟道区域中的应力诱导迁移率增强的方法，包括近似在通道中的多个采样点中的每一个处的应力，将每个采样点处的应力近似转换为相应的移动性增强值，并在所有采样点平均移动性增强值。该方法实现了集成电路应力分析，其考虑了由多个应力产生机制所产生的应力，具有沿通道长度以外的矢量分量的应力，以及由于在邻域中存在其它结构的应力贡献（包括缓解）正在研究的频道区域，除了最接近的STI接口。该方法还能够对大型布局区域甚至全芯片布局进行应力分析，而不会导致完整TCAD仿真的计算成本。

88. 发明授权

US08713510B2 Analysis of stress impact on transistor performance 有权
公开(公告)号：US08713510B2
公开(公告)日：2014-04-29
申请号：US12510185
申请日：2009-07-27
申请人： Victor Moroz , Dipankar Pramanik
发明人： Victor Moroz , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/5081
摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

89. 发明申请

US20130330412A1 SMART POLYMERIC NANOPARTICLES WHICH OVERCOME MULTIDRUG RESISTANCE TO CANCER THERAPEUTICS AND TREATMENT-RELATED SYSTEMIC TOXICITY 审中-公开
标题翻译：智能聚合纳米粒子，其具有多种抗癌性治疗和治疗相关系统毒性的作用
公开(公告)号：US20130330412A1
公开(公告)日：2013-12-12
申请号：US13992777
申请日：2011-12-08
申请人： Anirban Maitra , Dipankar Pramanik
发明人： Anirban Maitra , Dipankar Pramanik
IPC分类号： A61K9/51 , A61K45/06 , A61K31/704 , A61K31/12
CPC分类号： A61K31/12 , A61K9/0019 , A61K9/5138 , A61K31/704 , A61K31/7042 , A61K45/06 , C08F220/06 , C08F220/56 , C08F226/10 , A61K2300/00
摘要： Polymeric nanoparticles with a hydrophobic core that encapsulates curcumin and a hydrophilic shell with one or more chemotherapeutic agents (e.g., doxorubicin) associated with the shell surface are formed from N-isopropylacryl amide (NEPAAM), acrylic acid (AA), and at least one vinyl monomer selected from the group consisting of vinyl acetate, 4-vinyl benzoic acid, methylmethacrylate, vinylmethacrylate, N-vinylpyrrolidone, N-vinyl piperidone, N-vinyl caprolacum, N-vinyl carbazole, and styrene, where the NIPAAM, the AA, and the vinyl monomer are present at molar ratios of 50-70:10-30:10-30 for NIPAAM:AA:vinyl monomer. These nanoparticles effectively overcome multidrug resistance and ameliorate cardiomyopathy in vivo.
摘要翻译：具有与壳表面相关的一种或多种化学治疗剂（例如，多柔比星）封装姜黄素和亲水壳的疏水性核心的聚合物纳米颗粒由N-异丙基丙烯酰胺（NEPAAM），丙烯酸（AA）和至少一种乙烯基单体，选自乙酸乙烯酯，4-乙烯基苯甲酸，甲基丙烯酸甲酯，甲基丙烯酸乙烯酯，N-乙烯基吡咯烷酮，N-乙烯基哌啶酮，N-乙烯基caprolacum，N-乙烯基咔唑和苯乙烯，其中NIPAAM，AA，对于NIPAAM：AA：乙烯基单体，乙烯基单体的摩尔比为50-70:10-30:10-30。这些纳米粒子有效地克服了多药耐药，改善了体内心肌病。

90. 发明授权

US08572517B2 System and method for modifying a data set of a photomask 有权
标题翻译：用于修改光掩模的数据集的系统和方法
公开(公告)号：US08572517B2
公开(公告)日：2013-10-29
申请号：US12136277
申请日：2008-06-10
申请人： Dipankar Pramanik , Michiel Victor Paul Kruger , Roy V. Prasad , Abdurrahman Sezginer
发明人： Dipankar Pramanik , Michiel Victor Paul Kruger , Roy V. Prasad , Abdurrahman Sezginer
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/144 , G03F1/36
摘要： The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
摘要翻译：本发明提供了一种用于补偿将图案转移到集成电路层的不完备性的方法，通过使关于光掩模图案最小化成本函数，该成本函数量化电路参数的设计值和模拟值之间的偏差形成在半导体晶片上的图案。

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