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1. 发明授权

US5811346A Silicon corner rounding in shallow trench isolation process 失效
标题翻译：硅角圆化在浅沟槽隔离过程中
公开(公告)号：US5811346A
公开(公告)日：1998-09-22
申请号：US837161
申请日：1997-04-14
申请人： Harlan Sur , Olivier Laparra , Dipankar Pramanik
发明人： Harlan Sur , Olivier Laparra , Dipankar Pramanik
IPC分类号： H01L21/76 , H01L21/762 , H07L21/76
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A semiconductor device isolating structure and method for forming such a structure. In one embodiment, an opening is formed through a mask layer overlying a semiconductor substrate. A trench of a desired depth is then etched into the semiconductor substrate at the area of the semiconductor substrate underlying the opening in the mask layer. The trench is then filled with a dielectric material. After an oxide planarizing process, the present invention exposes the dielectric-filled trench to an oxidizing environment. By filling the trench with dielectric material prior to the oxidization step, the present invention selectively oxidizes the semiconductor substrate at corners formed by the intersection of the sidewalls of the trench and the top surface of the semiconductor substrate. In so doing, the present invention forms smoothly rounded semiconductor substrate corners under the mask layer. Thus, the present invention eliminates the sharp upper corners associated with prior art shallow trench isolation methods.
摘要翻译：一种用于形成这种结构的半导体器件隔离结构和方法。在一个实施例中，通过覆盖半导体衬底的掩模层形成开口。然后在掩模层中的开口下方的半导体衬底的区域处将期望深度的沟槽蚀刻到半导体衬底中。然后用电介质材料填充沟槽。在氧化物平面化处理之后，本发明将电介质填充的沟槽暴露于氧化环境。通过在氧化步骤之前用电介质材料填充沟槽，本发明在由沟槽的侧壁和半导体衬底的顶表面的相交处形成的拐角处选择性地氧化半导体衬底。这样做，本发明在掩模层下形成平滑的圆形半导体衬底拐角。因此，本发明消除了与现有技术的浅沟槽隔离方法相关联的尖锐的上角。

2. 发明授权

US09472423B2 Method for suppressing lattice defects in a semiconductor substrate 有权
标题翻译：抑制半导体衬底中的晶格缺陷的方法
公开(公告)号：US09472423B2
公开(公告)日：2016-10-18
申请号：US11928142
申请日：2007-10-30
申请人： Victor Moroz , Dipankar Pramanik
发明人： Victor Moroz , Dipankar Pramanik
IPC分类号： H01L21/324 , H01L21/265 , H01L29/10 , H01L29/78
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L29/1054 , H01L29/1079 , H01L29/7848
摘要： A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
摘要翻译：一种用于抑制在晶格中的掺杂剂注入之后的晶格中的渗漏促进缺陷的形成的方法。该方法提供原子的压缩层，这些原子的尺寸大于晶格构件原子的尺寸。然后将晶格退火足以使间隙缺陷原子从压缩层发射的时间，并且以这种方式，在离压缩层一定距离处的晶格中形成能量稳定的缺陷。

3. 发明申请

US20140055152A1 CIRCULAR TRANSMISSION LINE METHODS COMPATIBLE WITH COMBINATORIAL PROCESSING OF SEMICONDUCTORS 有权
标题翻译：圆形传输线方法与半导体的组合处理兼容
公开(公告)号：US20140055152A1
公开(公告)日：2014-02-27
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

4. 发明授权

US08637413B2 Nonvolatile resistive memory element with a passivated switching layer 有权
标题翻译：具有钝化开关层的非易失性电阻性存储元件
公开(公告)号：US08637413B2
公开(公告)日：2014-01-28
申请号：US13309813
申请日：2011-12-02
申请人： Charlene Chen , Dipankar Pramanik
发明人： Charlene Chen , Dipankar Pramanik
IPC分类号： H01L21/31 , H01L29/00 , G11C11/00
CPC分类号： H01L45/146 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.
摘要翻译：非易失性电阻存储元件具有新颖的可变电阻层，其在开关层沉积期间或之后被非金属掺杂剂原子如氮气钝化。可变电阻层中的非金属掺杂剂原子的存在使得开关层能够以降低的开关电流工作，同时保持改进的数据保持性能。

5. 发明授权

US08466446B2 Atomic layer deposition of metal oxide materials for memory applications 有权
公开(公告)号：US08466446B2
公开(公告)日：2013-06-18
申请号：US13612000
申请日：2012-09-12
申请人： Yun Wang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Tony Chiag
发明人： Yun Wang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik , Tony Chiag
IPC分类号： H01L47/00
CPC分类号： H01L45/145 , C23C16/40 , C23C16/45525 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/2463 , H01L45/08 , H01L45/1266 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

6. 发明授权

US08069430B2 Stress-managed revision of integrated circuit layouts 有权
标题翻译：集成电路布局的压力管理修订
公开(公告)号：US08069430B2
公开(公告)日：2011-11-29
申请号：US12546959
申请日：2009-08-25
申请人： Victor Moroz , Xi-Wei Lin , Dipankar Pramanik
发明人： Victor Moroz , Xi-Wei Lin , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L21/823807
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

7. 发明授权

US07897479B2 Managing integrated circuit stress using dummy diffusion regions 有权
标题翻译：使用虚拟扩散区管理集成电路应力
公开(公告)号：US07897479B2
公开(公告)日：2011-03-01
申请号：US12207349
申请日：2008-09-09
申请人： Xi-Wei Lin , Dipankar Pramanik , Victor Moroz
发明人： Xi-Wei Lin , Dipankar Pramanik , Victor Moroz
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823814 , H01L29/7846
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在至少N沟道晶体管的沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

8. 发明授权

US07895548B2 Filler cells for design optimization in a place-and-route system 有权
标题翻译：填充单元用于在路线和路径系统中进行设计优化
公开(公告)号：US07895548B2
公开(公告)日：2011-02-22
申请号：US11924738
申请日：2007-10-26
申请人： Xi Wei Lin , Jyh-Chwen Frank Lee , Dipankar Pramanik
发明人： Xi Wei Lin , Jyh-Chwen Frank Lee , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , H01L27/0207
摘要： A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.
摘要翻译：提供了一种系统和方法，用于将集成电路设计布置成具有间隙的多个电路布局单元，并且将至少一个子空间中的每个给定的一个插入到依赖于预定数据库的相应填充单元对所述给定间隙相邻的至少一个电路单元的性能参数产生期望的影响。电路布局单元可以排成行，并且在一些实施例中，用于给定间隙的适当填充单元的选择取决于与给定间隙相邻的两个电路单元的性能参数所期望的效果。预定义的填充单元可以包括例如虚拟扩散区域，虚拟多线，N阱边界位移和蚀刻停止层边界移位。在一个实施例中，可以移动电路布局单元以便容纳选定的填充单元。

9. 发明授权

US07739095B2 Method for determining best and worst cases for interconnects in timing analysis 有权
标题翻译：在时序分析中确定互连的最佳和最差情况的方法
公开(公告)号：US07739095B2
公开(公告)日：2010-06-15
申请号：US11685250
申请日：2007-03-13
申请人： Xi-Wei Lin , Dipankar Pramanik
发明人： Xi-Wei Lin , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd.
摘要翻译：粗略描述，在电路设计中为多个互连估计信号传播延迟值。对于每个互连，传播延迟值根据初步近似确定信号传播延迟是否由互连电容项或互连电容和电阻乘积项更多地支配来估计。如果更多地被互连电容项支配，则假定最小传播延迟计算使用的参数值是假定最小电容处理变化情况，并且假定最大电容处理变化获得用于最大传播延迟计算的参数值案件。如果信号传播延迟更多地被互连电容和电阻乘积项所主导，则进行相反的假设。优选地，通过将Rint与k * Rd进行比较来进行近似确定。

10. 发明申请

US20100023901A1 ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE 有权
公开(公告)号：US20100023901A1
公开(公告)日：2010-01-28
申请号：US12510188
申请日：2009-07-27
申请人： Victor Moroz , Dipankar Pramanik
发明人： Victor Moroz , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/5081
摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

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