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81. 发明申请

US20090096036A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090096036A1
公开(公告)日：2009-04-16
申请号：US12248250
申请日：2008-10-09
申请人： Takashi ISHIGAKI , Ryuta Tsuchiya , Yusuke Morita , Nobuyuki Sugii , Shinichiro Kimura , Toshiaki Iwamatsu
发明人： Takashi ISHIGAKI , Ryuta Tsuchiya , Yusuke Morita , Nobuyuki Sugii , Shinichiro Kimura , Toshiaki Iwamatsu
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26513 , H01L21/76283 , H01L21/823418 , H01L21/823481 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
摘要翻译：提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。第一升高层比升高的层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

82. 发明申请

US20090057746A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090057746A1
公开(公告)日：2009-03-05
申请号：US12187504
申请日：2008-08-07
申请人： Nobuyuki Sugll , Ryuta Tsuchiya , Shinichiro Kimura
发明人： Nobuyuki Sugll , Ryuta Tsuchiya , Shinichiro Kimura
IPC分类号： H01L29/788 , H01L29/06
CPC分类号： H01L27/1203 , H01L21/82385 , H01L21/823878 , H01L21/84 , H01L27/0207 , H01L27/0629 , H01L29/93
摘要： A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed on a surface of the SOI layer, a gate electrode formed on the gate dielectric, and a n+ type semiconductor region formed in the SOI layer located on both sides of the gate electrode. The MOS varactor, is configured so that capacitance formed by the SOI layer, gate dielectric, and gate electrode is varied by applying bias voltage to the supporting substrate (p type well) under the gate electrode.
摘要翻译：提供了一种具有无源元件的半导体器件，其特征是即使在通过施加反向偏置电压制造之后也是可调节的。在包括支撑衬底，BOX层和SOI层的SOI衬底的主表面上形成MOS变容二极管，其包括在SOI层的表面上形成的栅极电介质，形成在栅极电介质上的栅电极和 n +型半导体区域形成在位于栅电极两侧的SOI层中。 MOS变容二极管被配置为使得由SOI层，栅极电介质和栅电极形成的电容通过在栅电极下施加偏置电压到支撑衬底（p型阱）来改变。

83. 发明申请

US20070274144A1 Semiconductor Integrated Circuit Device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070274144A1
公开(公告)日：2007-11-29
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译：在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成比较器CP连接到预充电到高电压的匹配线HMLr。此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

84. 发明申请

US20050208716A1 Semiconductor integrated circuit device and production method thereof 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20050208716A1
公开(公告)日：2005-09-22
申请号：US11130236
申请日：2005-05-17
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L27/108 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L29/49
CPC分类号： H01L27/10894 , H01L21/76895 , H01L21/76897 , H01L21/823857 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L29/4941 , H01L29/6656
摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.
摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。结果，可以以自对准的方式降低硼渗透并形成接触电极。此外，可以提高构成逻辑电路的MISFET的性能。

85. 发明申请

US20050045933A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050045933A1
公开(公告)日：2005-03-03
申请号：US10914223
申请日：2004-08-10
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线，选择线。由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触，外围电路区域和存储单元区域之间的台阶高度显着降低。

86. 发明授权

US06831316B1 Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06831316B1
公开(公告)日：2004-12-14
申请号：US10009826
申请日：2002-03-19
申请人： Hideyuki Matsuoka , Takeshi Sakata , Shinichiro Kimura , Toshiaki Yamanaka , Tsuyoshi Kachi , Tomonori Sekiguchi
发明人： Hideyuki Matsuoka , Takeshi Sakata , Shinichiro Kimura , Toshiaki Yamanaka , Tsuyoshi Kachi , Tomonori Sekiguchi
IPC分类号： H01L4700
CPC分类号： H01L27/108 , H01L27/10894 , H01L27/10897
摘要： An existent DRAM memory cell comprises transistors as a switch and capacitors for accumulating storage charges in which the height of the capacitor has been increased more and more along with micro miniaturization, which directly leads to increase in the manufacturing cost. The invention of the present application provides a semiconductor memory device of a basic constitution in which a memory cell array having plural memory cells disposed on a semiconductor substrate and word lines and data lines for selecting the memory cells and a peripheral circuit at the periphery of the memory cell array wherein the memory cell comprises a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and a potential can be applied to the insulating layer enabling the tunneling effect. The invention of the present application concerns a memory cell not requiring capacitor and capable of being formed in simple steps.
摘要翻译：存在的DRAM存储单元包括作为开关的晶体管和用于累积存储电荷的电容器，其中电容器的高度随着微型化而逐渐增加，这直接导致制造成本的增加。本申请的发明提供了一种基本结构的半导体存储器件，其中具有设置在半导体衬底上的多个存储单元的存储单元阵列和用于选择存储单元的字线和数据线以及外围电路的外围电路存储单元阵列，其中存储单元包括导电层的多层，绝缘层和含有杂质的多个半导体层，并且可以将电位施加到能够实现隧道效应的绝缘层。本申请的发明涉及不需要电容器并能够以简单的步骤形成的存储单元。

87. 发明授权

US06812540B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06812540B2
公开(公告)日：2004-11-02
申请号：US10298682
申请日：2002-11-19
申请人： Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L2900
CPC分类号： H01L27/105 , H01L27/10897
摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.
摘要翻译：提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对用于构成读出放大器。假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差可以减少MISFET对。

88. 发明授权

US06535435B2 Reference voltage generator permitting stable operation 有权
标题翻译：参考电压发生器允许稳定运行
公开(公告)号：US06535435B2
公开(公告)日：2003-03-18
申请号：US10012522
申请日：2001-12-12
申请人： Hitoshi Tanaka , Masakazu Aoki , Shinichiro Kimura , Hiromasa Noda , Tomonori Sekiguchi
发明人： Hitoshi Tanaka , Masakazu Aoki , Shinichiro Kimura , Hiromasa Noda , Tomonori Sekiguchi
IPC分类号： G11C700
CPC分类号： H01L27/0222 , G11C5/145 , G11C5/147 , G11C11/4074 , H01L27/10897
摘要： A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.
摘要翻译：提供了一种参考电压产生电路，其包括用作输入晶体管的p沟道型MOSFET，以允许足够的电流流过差分放大器，即使差分放大器中使用的MOSFET的阈值电压显着增加。推挽转换电路耦合到差分放大器并且具有双端配置以提供足够高的电平来驱动p沟道输出缓冲器。即使形成差分放大器的MOSFET的阈值电压高，这种布置允许在足够低的电源电压下的稳定操作。它还允许在电源打开时快速启动并提供高稳定性。

89. 发明授权

US06376304B1 Semiconductor memory device and a method for fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06376304B1
公开(公告)日：2002-04-23
申请号：US09608154
申请日：2000-06-30
申请人： Hideyuki Matsuoka , Shinichiro Kimura , Toshiaki Yamanaka
发明人： Hideyuki Matsuoka , Shinichiro Kimura , Toshiaki Yamanaka
IPC分类号： H01L218242
CPC分类号： H01L27/10882 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed; therefore, a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied. Besides, interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, the filling up of the holes with metal and the like are unnecessary and, as a result, reliability of the process is improved.
摘要翻译：提供一种半导体存储器件及其制造方法，其中在外围电路区域之上形成仅覆盖存储单元阵列外的外围电路区域的层间膜，以减少在形成位线之后的两个区域之间的拓扑差异 ; 因此，以普通表面为主要的半导体衬底可以用作起始体，而不需要预处理，也可以应用浅沟槽隔离技术。此外，与外围电路的互连可以通过多级插头连接引导到设备的表面，从而处理大的纵横比孔，用金属填充孔等是不必要的，因为结果，改进了该过程的可靠性。

90. 发明授权

US6157055A Semiconductor memory device having a long data retention time with the increase in leakage current suppressed 失效
标题翻译：具有抑制了泄漏电流增加的数据保持时间长的半导体存储器件
公开(公告)号：US6157055A
公开(公告)日：2000-12-05
申请号：US185633
申请日：1998-11-04
申请人： Ken Yamaguchi , Shinichiro Kimura , Masatada Horiuchi , Tatsuya Teshima
发明人： Ken Yamaguchi , Shinichiro Kimura , Masatada Horiuchi , Tatsuya Teshima
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L27/10808 , H01L27/10873
摘要： In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with a thin insulating film in between. This conductive film (1.11') is electrically connected to a lower electrode (1.11) of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.
摘要翻译：在诸如DRAM的半导体存储器件中，在隔离绝缘膜（1.2）的与半导体衬底（1.1）相对的边缘部分上布置导电膜（1.11'），其间具有薄的绝缘膜。该导电膜（1.11'）电连接到存储电容器的下电极（1.11）。这种新颖的布置可以独立于冶金pn结的位置来控制电pn结的位置，从而实现了抑制泄漏电流增加的数据保持时间长的半导体存储器件。

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