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81. 发明授权

US6096643A Method of fabricating a semiconductor device having polysilicon line with extended silicide layer 失效
标题翻译：制造具有多晶硅线的半导体器件的方法，该多晶硅线具有延伸的硅化物层
公开(公告)号：US6096643A
公开(公告)日：2000-08-01
申请号：US164956
申请日：1998-10-01
申请人： Homi E. Nariman , H. Jim Fulford , Charles E. May
发明人： Homi E. Nariman , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76885 , H01L21/76889 , H01L21/76895
摘要： A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.
摘要翻译：提供了半导体器件和制造工艺，其中多晶硅线路设置在半导体器件的衬底上。多晶硅线可以例如是栅电极。电介质层设置在多晶硅线附近并且在多晶硅线上形成延伸的硅化物层。可以通过在多晶硅线上形成图案化的金属层，在图案化的金属层上形成多晶硅层，并使图案化的金属层与多晶硅层反应以在多晶硅线上形成延伸的硅化物层来形成延伸的硅化物层。器件还可以包括第二多晶硅线，例如栅电极，并且硅化物层可以在第二多晶硅线的顶部上延伸并互连两个多晶硅线。

82. 发明授权

US5904534A Transistor formation with local interconnect overetch immunity 有权
标题翻译：晶体管形成与局部互连overetch免疫
公开(公告)号：US5904534A
公开(公告)日：1999-05-18
申请号：US134702
申请日：1998-08-14
申请人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/762 , H01L21/768 , H01L21/336 , H01L21/76
CPC分类号： H01L21/76895 , H01L21/76224
摘要： An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.
摘要翻译：提供一种集成电路晶体管及其制造方法。晶体管由于局部互连沟槽的过蚀刻而抵抗结短路。该晶体管包括具有第一结的源极/漏极区域和位于有源区域的易于经过过渡接合短路现象的部分中比第一结点更深的第二结点。第二结通过通过掩模的离子注入建立，其被图案化以产生对应于有源区和局部互连沟槽的布局的相交的开口。使用该方法，仅在需要防止短路并且不妨碍晶体管性能的情况下才建立第二结。

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