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81. 发明申请

US20120292701A1 Silicon on Insulator Field Effect Device 审中-公开
标题翻译：硅绝缘体场效应器件
公开(公告)号：US20120292701A1
公开(公告)日：2012-11-22
申请号：US13557370
申请日：2012-07-25
申请人： Dechao Guo , Zhen Zhang
发明人： Dechao Guo , Zhen Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/66545 , H01L29/66621 , H01L29/66628
摘要： A field effect transistor device includes a silicon on insulator (SOI) body portion disposed on a buried oxide (BOX) substrate, a gate stack portion disposed on the SOI body portion, a first silicide material disposed on the BOX substrate, the first silicide material arranged adjacent to the gate stack portion, a second silicide material arranged on the first silicide material, a source region including a portion of the first silicide material and the second silicide material, and a drain region including a portion of the first silicide material and the second silicide material.
摘要翻译：场效应晶体管器件包括设置在掩埋氧化物（BOX）衬底上的绝缘体上硅（SOI）体部分，设置在SOI主体部分上的栅堆叠部分，设置在BOX衬底上的第一硅化物材料，第一硅化物材料排列在所述第一硅化物材料上的第二硅化物材料，包括所述第一硅化物材料和所述第二硅化物材料的一部分的源区，以及包含所述第一硅化物材料的一部分的漏区，以及第二硅化物材料。

82. 发明授权

US08309418B2 Field effect transistor device with shaped conduction channel 有权
标题翻译：具有形状导通通道的场效应晶体管器件
公开(公告)号：US08309418B2
公开(公告)日：2012-11-13
申请号：US12860977
申请日：2010-08-23
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/4236 , H01L29/66621
摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
摘要翻译：场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料，填充空腔的金属栅极材料，源极区域和漏极区域。

83. 发明申请

US20120256294A1 Nanopillar Decoupling Capacitor 有权
标题翻译：纳米棒去耦电容器
公开(公告)号：US20120256294A1
公开(公告)日：2012-10-11
申请号：US13530549
申请日：2012-06-22
申请人： Satya N. Chakravarti , Dechao Guo , Huiming Bu , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Huiming Bu , Keith Kwong Hon Wong
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： B82Y10/00 , H01L21/8221 , H01L23/5223 , H01L27/0688 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.
摘要翻译：提供了将纳米技术纳入去耦电容器设计的技术。在一个方面，提供去耦电容器。去耦电容器包括第一电极; 与第一电极相邻的中间层，其中具有多个纳米通道; 在中间层上形成并衬在纳米通道上的保形介电层; 以及第二电极，其至少一部分由填充中间层中的纳米通道的纳米柱阵列形成。还提供了用于制造去耦电容器的方法，以及包含去耦电容器设计的半导体器件。

84. 发明申请

US20120235247A1 FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING 有权
标题翻译：具有用于阈值电压调谐的可变通道厚度的FIN场效应晶体管
公开(公告)号：US20120235247A1
公开(公告)日：2012-09-20
申请号：US13050101
申请日：2011-03-17
申请人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chung-hsun Lin , Chun-chen Yeh
IPC分类号： H01L27/088 , H01L21/32
CPC分类号： H01L27/0886 , H01L21/3086 , H01L21/845 , H01L27/1211
摘要： A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
摘要翻译：一种形成集成电路（IC）的方法包括在基板上形成第一和第二多个间隔物，其中所述基板包括硅层，并且其中所述第一多个间隔件的厚度不同于所述第二多个间隔物; 并且使用所述第一和第二多个间隔物作为掩模来蚀刻所述衬底中的所述硅层，其中所述蚀刻的硅层形成第一多个和第二多个鳍状场效应晶体管（FINFET）沟道区，并且其中所述第一多个 FINFET通道区域各自具有对应于第一多个间隔物的厚度的相应厚度，并且其中第二多个FINFET沟道区域各自具有对应于第二多个间隔物的厚度的相应厚度。

85. 发明申请

US20120119266A1 Stressor in Planar Field Effect Transistor Device 失效
标题翻译：平面场效应晶体管器件中的应力器
公开(公告)号：US20120119266A1
公开(公告)日：2012-05-17
申请号：US12945026
申请日：2010-11-12
申请人： Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Alexander Reznicek , Keith Kwong Hon Wong
发明人： Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Alexander Reznicek , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/1054 , H01L29/66477 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.
摘要翻译：场效应晶体管器件包括设置在衬底上的栅极堆叠部分和衬底中的沟道区域，其具有由栅极堆叠部分和衬底的硅区域部分地限定的深度，所述硅区域具有倾斜轮廓，使得沟道区域的远侧区域具有比沟道区域的中间区域更深的深度。

86. 发明申请

US20120061772A1 Transistor having replacement metal gate and process for fabricating the same 有权
标题翻译：具有替代金属栅极的晶体管及其制造方法
公开(公告)号：US20120061772A1
公开(公告)日：2012-03-15
申请号：US12880085
申请日：2010-09-11
申请人： Dechao Guo , Keith Kwong Hon Wong
发明人： Dechao Guo , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28079 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/42372 , H01L29/517 , H01L29/66545
摘要： A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.
摘要翻译：通过在衬底的掺杂区域上去除多晶硅栅极并在衬底上形成掩模层来制造晶体管，使得掺杂区域通过掩模层内的孔露出。界面层沉积在掩模层的顶表面和侧表面上以及在掺杂区的顶表面上。适于降低晶体管的阈值电压和/或降低晶体管的反型层的厚度的层被沉积在界面层上。该层包括扩散到界面层中的金属，例如铝或镧，并且还包括氧化物，例如氧化铪。在掩模层的孔内形成导电塞，例如金属塞。界面层，界面层上的层和导电插塞是晶体管的替代栅极。

87. 发明申请

US20120038008A1 Field Effect Transistor Device with Self-Aligned Junction and Spacer 审中-公开
标题翻译：具有自对准结和间隔的场效应晶体管器件
公开(公告)号：US20120038008A1
公开(公告)日：2012-02-16
申请号：US12857017
申请日：2010-08-16
申请人： Dechao Guo , Pranita Kulkarni , Ramachandran Muralidhar , Chun-Chen Yeh
发明人： Dechao Guo , Pranita Kulkarni , Ramachandran Muralidhar , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7834
摘要： In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate.
摘要翻译：在本发明的一个方面中，一种用于制造场效应晶体管器件的方法包括在衬底的第一部分上形成虚拟栅叠层，形成与虚栅极堆叠相邻的源区和漏区，形成离子掺杂源极延伸部分，在衬底中形成离子掺杂的漏极延伸部分，形成与虚拟栅极堆叠相邻的第一间隔部分，去除伪栅极堆叠以暴露衬底的沟道区域，一部分离子掺杂源极延伸部分和离子掺杂漏极延伸部分的一部分，在离子掺杂源极延伸部分的暴露部分上以及在离子掺杂漏极延伸部分的暴露部分上形成第二间隔部分，并形成栅叠层衬底的暴露的沟道区域。

88. 发明申请

US20120038007A1 Field Effect Transistor Device With Self-Aligned Junction 审中-公开
标题翻译：具有自对准结的场效应晶体管器件
公开(公告)号：US20120038007A1
公开(公告)日：2012-02-16
申请号：US12857013
申请日：2010-08-16
申请人： Dechao Guo , Pranita Kulkarni , Ramachandran Muralidhar , Chun-Chen Yeh
发明人： Dechao Guo , Pranita Kulkarni , Ramachandran Muralidhar , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/66537 , H01L29/66575 , H01L29/7833
摘要： A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底的第一部分上形成虚拟栅叠层，形成与虚栅极叠层相邻的源区和漏区，在衬底中形成离子掺杂源延伸部分，源极延伸部分，从源极区域延伸到衬底的第一部分中，在衬底中形成离子掺杂漏极延伸部分，漏极延伸部分从漏极区域延伸到衬底的第一部分中，去除虚部的一部分栅极堆叠以暴露伪栅极堆叠的界面层，在源延伸部分和漏极延伸部分中注入离子，以在衬底的第一部分中形成沟道区域，去除界面层，以及在栅极叠层上形成栅叠层沟道区域。

89. 发明申请

US20110115022A1 IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES 有权
标题翻译：嵌入式无限超薄半导体器件
公开(公告)号：US20110115022A1
公开(公告)日：2011-05-19
申请号：US12621299
申请日：2009-11-18
申请人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers.
摘要翻译：公开了半导体器件和制造半导体器件的方法。在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。以这种方式，半导体层成为非常薄的绝缘体上半导体层。在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。在Ge层上外延生长极薄的半导体层确保跨晶片的良好的厚度控制。该工艺可用于SOI或体晶片。

90. 发明申请

US20110083786A1 ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES 失效
标题翻译：用于基板之间的平面结合的自适应块
公开(公告)号：US20110083786A1
公开(公告)日：2011-04-14
申请号：US12575968
申请日：2009-10-08
申请人： Dechao Guo , Fei Liu , Leathen Shi , Keith Kwong Hon Wong
发明人： Dechao Guo , Fei Liu , Leathen Shi , Keith Kwong Hon Wong
IPC分类号： B29C65/78 , H01L21/683
CPC分类号： H01L21/6833 , B32B37/0007 , B32B2457/14 , Y10T156/1002
摘要： An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.
摘要翻译：静电卡盘包括独立偏置的导电卡盘元件的阵列，传感器 - 导体组件的阵列，和/或传感器 - 导体组件阵列和至少一个电动卡盘的组合。独立地或嵌入传感器 - 导体组件中的导电卡盘元件被静电地独立地偏置以补偿其上的衬底的弯曲和/或翘曲，使得衬底可以与平坦表面结合。可以使用单个静电卡盘来减少要接合的两个基板中的一个的弯曲和翘曲，或者可以使用两个静电卡盘来最小化要接合的两个基板的弯曲和翘曲。

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