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81. 发明授权

US5981404A Multilayer ONO structure 失效
标题翻译：多层ONO结构
公开(公告)号：US5981404A
公开(公告)日：1999-11-09
申请号：US857734
申请日：1997-05-16
申请人： Yi Chung Sheng , Yi Chih Lim , Ming Hua Liu , Ming-Tzong Yang
发明人： Yi Chung Sheng , Yi Chih Lim , Ming Hua Liu , Ming-Tzong Yang
IPC分类号： H01L21/28 , H01L21/314 , H01L29/51 , H01L29/68
CPC分类号： H01L21/28202 , H01L21/28238 , H01L21/3145 , H01L29/513 , H01L29/518 , Y10S438/954
摘要： Dielectric structures of the type that might be used in DRAMs, other memory devices, and integrated thin film transistors include repeated silicon oxide/silicon nitride layers. For example, the dielectric structure may have a silicon oxide/silicon nitride/silicon oxide/silicon nitride/silicon oxide or "ONONO" layer structure. Such repeated layer structures exhibit higher levels of breakdown voltage than more conventional "ONO" structures. Most of the growth of the five layer ONONO or more complicated dielectric structure can be accomplished in a single furnace through a series of temperature steps performed under different gas ambients. A substrate having a polysilicon lower electrode is introduced to a furnace and a lowest layer of silicon oxide is grown on the polysilicon electrode in an ammonia ambient. A first silicon nitride layer is grown in NH.sub.3 and SiH.sub.2 Cl.sub.2 and then growth of the first silicon nitride layer is interrupted by first altering or stopping the flow of reaction gases and then growing an intermediate silicon oxide layer on the first silicon nitride layer, again in an ammonia ambient. A second silicon nitride layer is then formed by reintroducing the same combination of processing gases. Growth of the second silicon nitride layer is then interrupted, and either additional repetitions of the silicon oxide/silicon nitride layer structure are formed or a surface layer of silicon oxide is grown in a steam or wet oxygen ambient.
摘要翻译：可能用于DRAM，其他存储器件和集成薄膜晶体管的类型的介质结构包括重复的氧化硅/氮化硅层。例如，电介质结构可以具有氧化硅/氮化硅/氧化硅/氮化硅/氧化硅或“ONONO”层结构。这种重复的层结构表现出比更传统的“ONO”结构更高的击穿电压水平。通过在不同气体环境下进行的一系列温度步骤，可以在单个炉中实现五层ONONO或更复杂的电介质结构的大部分生长。将具有多晶硅下电极的基板引入炉中，并且在氨气氛中在多晶硅电极上生长最低层的氧化硅。第一氮化硅层生长在NH 3和SiH 2 Cl 2中，然后通过首先改变或停止反应气体的流动然后在第一氮化硅层上再生长中间氧化硅层，从而中断第一氮化硅层的生长氨气。然后通过重新引入相同的处理气体组合来形成第二氮化硅层。然后中断第二氮化硅层的生长，并且形成氧化硅/氮化硅层结构的附加重复，或者在蒸汽或湿氧环境中生长氧化硅的表面层。

82. 发明授权

US5798298A Method of automatically generating dummy metals for multilevel interconnection 失效
标题翻译：自动生成多层互连的虚拟金属的方法
公开(公告)号：US5798298A
公开(公告)日：1998-08-25
申请号：US598802
申请日：1996-02-09
申请人： Ming-Tzong Yang , Hong-Tsz Pan
发明人： Ming-Tzong Yang , Hong-Tsz Pan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/28
CPC分类号： H01L23/522 , H01L21/76819 , H01L21/76838 , H01L2924/0002 , Y10S438/926
摘要： A method of automatically generating dummy metals for multilevel interconnection makes use of a quantum array pattern accompanying an operating pattern to from a metal pattern. The method comprises the combination selected from intersection (AND), union (OR), oversizing, downsizing, or incorporation operation through computer-aided design (CAD). Therefore, the application of the metal pattern to a process for fabricating a multimetal structure can acquire full planarization between two metal layers because of the arrangement that several dummy metals are positioned among the metal lines to diminish the spacing which exceeds the planarization limit. Also, the dummy metals are shaped in blocks thereby preventing the loading effect during etching and decreasing the parasitic capacitance therebetween.
摘要翻译：自动生成用于多层互连的虚拟金属的方法利用伴随着来自金属图案的操作图案的量子阵列图案。该方法包括通过计算机辅助设计（CAD）从交叉（AND），联合（OR），超大尺寸，缩小尺寸或并入操作中选择的组合。因此，金属图案在制造多金属结构的工艺中的应用可以获得两个金属层之间的完全平坦化，这是因为在金属线之间布置了若干虚拟金属以减少超过平坦化极限的间隔。此外，虚拟金属成块状，从而防止蚀刻期间的负载效应并降低它们之间的寄生电容。

83. 发明授权

US5712500A Multiple cell with common bit line contact and method of manufacture thereof 失效
标题翻译：具有通用位线接触的多单元及其制造方法
公开(公告)号：US5712500A
公开(公告)日：1998-01-27
申请号：US556326
申请日：1996-02-26
申请人： Chen-Chiu Hsue , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Ming-Tzong Yang
IPC分类号： H01L21/768 , H01L23/528 , H01L29/788
CPC分类号： H01L23/5283 , H01L21/768 , H01L2924/0002
摘要： In accordance with this invention, a method of manufacture of a semiconductor memory device comprises the following steps: forming field oxide structures on a semiconductor substrate, forming a gate oxide layer on exposed surfaces of the substrate, forming a first word line layer on the device, patterning the first word line layer by forming a first patterned mask mask with a first set of openings therein and etching the first word line layer through the openings in the first mask to form conductor lines, forming a first dielectric layer on the surface of the first word line layer on the device, forming a second word line layer on the first dielectric layer, patterning the second word line layer by forming a second patterned mask with a second set of openings therein and etching portions of the second word line layer therethrough, h) forming a second dielectric layer on the surface of the second word line layer on the device, and implanting ions of dopant into predetermined locations into the semiconductor substrate of the device, the dopant being of sufficient concentration to form a doped region therein.
摘要翻译：根据本发明，半导体存储器件的制造方法包括以下步骤：在半导体衬底上形成场氧化物结构，在衬底的暴露表面上形成栅氧化层，在器件上形成第一字线层通过在其中形成具有第一组开口的第一图案化掩模掩模来形成第一字线层，并通过第一掩模中的开口蚀刻第一字线层以形成导体线，在第一掩模掩模的表面上形成第一介电层在所述器件上的第一字线层，在所述第一电介质层上形成第二字线层，通过在其中形成具有第二组开口的第二组开口形成第二图案化掩模来构图所述第二字线层，并且通过其蚀刻所述第二字线层的部分， h）在所述器件上的所述第二字线层的表面上形成第二电介质层，以及将掺杂剂的离子注入预定位置i n到器件的半导体衬底，掺杂剂具有足够的浓度以在其中形成掺杂区域。

84. 发明授权

US5650657A Protection from short circuits between P and N wells 失效
标题翻译：保护P和N井之间的短路
公开(公告)号：US5650657A
公开(公告)日：1997-07-22
申请号：US347680
申请日：1994-12-01
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L21/8238 , H01L27/082 , H01L27/092 , H01L27/105 , H01L29/76 , H01L29/94
CPC分类号： H01L21/823892 , H01L27/0821 , H01L27/0928 , H01L27/105 , Y10S148/07
摘要： A method of manufacture of a MOSFET device with a predetermined light positive or negative doping comprises forming a first mask upon said substrate. Dopant of a predetermined positive or negative variety is implanted through the mask. A second mask is formed over the openings in the first mask. The first mask is removed. Dopant of the opposite positive or negative variety is implanted into the openings in the second mask. The process forms a pattern of positive and negative wells in the substrate, and forms a guard ring of an opposite doping variety from the wells being protected formed in the substrate.
摘要翻译：具有预定的光正或负掺杂的MOSFET器件的制造方法包括在所述衬底上形成第一掩模。通过掩模注入预定的正或负品种的掺杂剂。在第一掩模的开口上方形成第二掩模。第一个面具被删除。相反的正或负品种的掺杂剂植入第二掩模的开口中。该方法在衬底中形成正和负阱的图案，并形成与被保护形成在衬底中的阱相反的掺杂种类的保护环。

85. 发明授权

US5591549A Self aligning fabrication method for sub-resolution phase shift mask 失效
标题翻译：用于亚分辨率相移掩模的自对准制造方法
公开(公告)号：US5591549A
公开(公告)日：1997-01-07
申请号：US307232
申请日：1994-09-16
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： G03F1/29 , G03F7/12
CPC分类号： G03F1/29
摘要： The invention describes the fabrication and use of a sub-resolution phase shift mask. The mask is formed using a single alignment step with all other alignment steps being accomplished by self alignment. This self alignment is made possible by using vertical anisotropic etching of an opaque material layer to form opaque spacers at the pattern edges of phase shifting material. The opaque spacers combine with phase shifting and other opaque regions of the mask to provide improved image resolution and depth of focus tolerance at the surface of an integrated circuit wafer.
摘要翻译：本发明描述了亚分辨率相移掩模的制造和使用。使用单个对准步骤形成掩模，所有其它对准步骤通过自对准完成。通过使用不透明材料层的垂直各向异性蚀刻在相移材料的图案边缘处形成不透明间隔物，可以实现这种自对准。不透明的间隔物与掩模的相移和其他不透明区域结合，以在集成电路晶片的表面提供改善的图像分辨率和聚焦容限深度。

86. 发明授权

US5569962A Split polysilicon SRAM cell 失效
标题翻译：分离多晶硅SRAM单元
公开(公告)号：US5569962A
公开(公告)日：1996-10-29
申请号：US341940
申请日：1994-11-16
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L21/8244 , H01L27/11 , H01L23/48 , H01L29/78
CPC分类号： H01L27/1108 , H01L27/11 , H01L27/1112 , Y10S257/90 , Y10S257/904
摘要： An SRAM semiconductor device comprises a first layer, a second layer and a third layer of polysilicon are separated by dielectric layers formed on a substrate, and a split gate structure with transistors formed in different polysilicon levels. Preferably, the split gate structure includes pull down transistors and pass gate transistors formed in different polysilicon levels; the second polysilicon layer extends into contact with the substrate; the second polysilicon layer contacts the third polysilicon layer in an interconnection region; and the third polysilicon layer comprises a polysilicon load resistor.
摘要翻译：包括第一层，第二层和第三多晶硅层的SRAM半导体器件由形成在衬底上的电介质层分离，并且具有以不同多晶硅层形成的晶体管的分离栅极结构。优选地，分离栅极结构包括形成在不同多晶硅层中的下拉晶体管和栅极晶体管; 第二多晶硅层延伸成与基板接触; 第二多晶硅层在互连区域中接触第三多晶硅层; 并且第三多晶硅层包括多晶硅负载电阻器。

87. 发明授权

US5516713A Method of making high coupling ratio NAND type flash memory 失效
标题翻译：制造高耦合率NAND型闪存的方法
公开(公告)号：US5516713A
公开(公告)日：1996-05-14
申请号：US301533
申请日：1994-09-06
申请人： Chen-Chiu Hsue , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Ming-Tzong Yang
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A new method of fabricating a high coupling ratio Flash EEPROM memory cell is described. A layer of silicon dioxide is grown over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. The silicon dioxide layer not covered by the patterned silicon nitride layer and the silicon nitride spacers is removed thereby exposing portions of the semiconductor substrate as tunneling windows. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer which is patterned to form a control gate. Passivation and metallization complete the fabrication of the NAND type memory cell with improved coupling ratio.
摘要翻译：描述了制造高耦合比闪存EEPROM存储单元的新方法。在半导体衬底的表面上生长一层二氧化硅。一层氮化硅沉积在二氧化硅层上并构图。在图案化氮化硅层的侧壁上形成氮化硅间隔物。未图案化的氮化硅层和氮化硅间隔层被覆盖的二氧化硅层被去除，从而将半导体衬底的部分暴露为隧道窗。在半导体衬底的暴露部分上生长隧道氧化物层。去除氮化硅层和间隔物。第一多晶硅层沉积在二氧化硅和隧道氧化物层的表面上并被图案化以形成浮栅。在图案化的第一多晶硅层上沉积多层介电层，随后是第二多晶硅层，其被图案化以形成控制栅极。钝化和金属化完成了具有改进的耦合比的NAND型存储单元的制造。

88. 发明授权

US5482900A Method for forming a metallurgy system having a dielectric layer that is planar and void free 失效
标题翻译：用于形成具有平坦且无空隙的介电层的冶金系统的方法
公开(公告)号：US5482900A
公开(公告)日：1996-01-09
申请号：US307233
申请日：1994-09-16
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L21/768 , H01L21/465
CPC分类号： H01L21/76837 , H01L21/76834
摘要： A process where a blanket metal layer and a blanket SiO.sub.2 layer are formed on the surface of a semiconductor substrate. A metallurgy pattern is formed in the metal and SiO.sub.2 layers, and a thin conformal SiO.sub.2 layer formed over the metallurgy pattern. A relatively thick non-conformal SOG layer of insulating material is formed over the Si).sub.2 layer, which is etched back. Subsequently a relatively thick CVD layer is deposited on the surface. The steps are repeated to form additional metallurgy levels.
摘要翻译：在半导体衬底的表面上形成覆盖金属层和覆盖层SiO 2层的工艺。在金属和SiO2层中形成冶金图案，在冶金图案上形成薄的共形SiO 2层。在Si 2层上形成相对较厚的非共形SOG绝缘材料层，其被回蚀刻。随后在表面上沉积相对较厚的CVD层。重复这些步骤以形成额外的冶金水平。

89. 发明授权

US5478678A Double rim phase shifter mask 失效
标题翻译：双圈移相器面罩
公开(公告)号：US5478678A
公开(公告)日：1995-12-26
申请号：US318426
申请日：1994-10-05
申请人： Ming-Tzong Yang , Hong-Tsz Pan
发明人： Ming-Tzong Yang , Hong-Tsz Pan
IPC分类号： G03F1/29 , G03F9/00
CPC分类号： G03F1/29
摘要： This invention describes the fabrication and use of a double rim phase shifter mask comprised of patterned layers of phase shifting material, partially transmitting material, and opaque material formed on a transparent substrate. Since the partially transmitting material is used as a rim at the pattern edge the light intensity transmitted to the wafer is not limited by the transmitting percentage of the partially transmitting material. The mask is self aligned and is readily manufacturable. Image resolution and depth of focus is improved over other photomasks.
摘要翻译：本发明描述了由相移材料的图案化层，部分透光材料和形成在透明衬底上的不透明材料组成的双边缘移相器掩模的制造和使用。由于部分透射材料在图案边缘被用作边缘，所以传输到晶片的光强度不受部分透射材料的透射百分比的限制。面具是自对准的，并且易于制造。与其他光掩模相比，图像分辨率和焦深得到改善。

90. 发明授权

US5461251A Symmetric SRAM cell with buried N+ local interconnection line 失效
标题翻译：具有埋地N +局部互连线的对称SRAM单元
公开(公告)号：US5461251A
公开(公告)日：1995-10-24
申请号：US294850
申请日：1994-08-29
申请人： Ming-Tzong Yang , Chen-Chiu Hsue
发明人： Ming-Tzong Yang , Chen-Chiu Hsue
IPC分类号： H01L23/535 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1108 , H01L23/535 , H01L27/11 , H01L27/1112 , H01L2924/0002 , Y10S257/903
摘要： A symmetrical, SRAM silicon device comprises a substrate comprising a semiconductor material with, a set of buried local interconnection lines in the silicon substrate. A word line is located centrally on the surface of the device. Pull down transistors are located symmetrically one either side of the word line. Interconnections are formed in the same layer as a BN+ diffusion. There is only one wordline composed of polysilicon. The pull down transistors are located on opposite sides of the word line. The cell size is small. There is no 45.degree. layout, and the metal rule is loose. Pass transistor source and drain regions are formed in the substrate juxtaposed with the buried local interconnection line. There is a layer of gate oxide above the source region and the drain region, and a gate above the gate oxide juxtaposed with the source region and drain region.
摘要翻译：一种对称的SRAM硅器件包括一个衬底，该衬底包括半导体材料，该硅衬底具有一组掩埋的局部互连线。字线位于设备表面的中央。下拉晶体管对称地位于字线的任一侧。互连在与BN +扩散相同的层中形成。只有一条由多晶硅组成的字线。下拉晶体管位于字线的相对侧。电池尺寸很小没有45°布局，金属规则松散。在与掩埋的局部互连线并置的衬底中形成通过晶体管源极和漏极区。在源极区和漏极区上方有一层栅极氧化物，并且栅极氧化物上方的栅极与源极区和漏极区并置。

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