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81. 发明授权

US5334281A Method of forming thin silicon mesas having uniform thickness 失效
标题翻译：形成厚度均匀的薄硅台面的方法
公开(公告)号：US5334281A
公开(公告)日：1994-08-02
申请号：US876598
申请日：1992-04-30
申请人： George W. Doerre , Seiki Ogura , Nivo Rovedo
发明人： George W. Doerre , Seiki Ogura , Nivo Rovedo
IPC分类号： H01L21/304 , H01L21/306 , H01L21/3105 , H01L21/321 , H01L21/76 , H01L21/762 , H01L27/12 , H01L21/08
CPC分类号： H01L21/76251 , H01L21/31053 , H01L21/32105 , Y10S148/05 , Y10S438/97
摘要： An SOI wafer has a device layer of initial thickness that is formed into a set of mesas in the interval between which a temporary layer of polysilicon is deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop having a thickness much smaller than the initial thickness. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide is not removed but serves both as an isolating layer to provide dielectric isolation between mesas in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.
摘要翻译： SOI晶片具有初始厚度的器件层，其在其间沉积有临时多晶硅层的区域中形成一组台面，以精确控制的厚度。该多晶硅在自限制过程中被完全转换成具有远小于初始厚度的厚度的氧化物蚀刻停止。通过化学机械抛光技术使台面变薄，直到台面与新氧化物的顶表面相同。氧化物的蚀刻停止层不被去除，而是用作隔离层，以在最终电路中的台面之间提供介电隔离，并且还用作可视仪器以确定抛光过程应该停止的时间。

82. 发明授权

US4982257A Vertical bipolar transistor with collector and base extensions 失效
标题翻译：具有集电极和基极延伸的垂直双极晶体管
公开(公告)号：US4982257A
公开(公告)日：1991-01-01
申请号：US452450
申请日：1989-12-19
申请人： Shah Akbar , Patricia L. Kroesen , Seiki Ogura , Nivo Rovedo
发明人： Shah Akbar , Patricia L. Kroesen , Seiki Ogura , Nivo Rovedo
IPC分类号： H01L21/331 , H01L29/08 , H01L29/10 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/1004 , H01L29/732
摘要： A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with an extending laterally from another side of the base layer. The structure further includes a base contact interconnect disposed on a surface of the base contact extension layer and; a collector contact extension layer formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.
摘要翻译：压缩的垂直双极晶体管配置，消除了标准对称基极接触的一侧，同时也消除了对集电极触点的要求。双极晶体管包括：集电极层; 设置在所述集电极层上的基层; 设置在所述基底层上的发射极层; 邻近并与发射极层，基极层和集电极层的至少一部分接触的第一侧壁绝缘层; 第二侧壁绝缘层，邻近并与发射极层的另一侧接触并且与基底层的至少一部分接触; 以及由与所述基底层相同导电类型的重掺杂半导体材料形成的基底接触延伸层，所述基底接触延伸层与从所述基底层的另一侧横向延伸接触。所述结构还包括设置在所述基部接触延伸层的表面上的基极接触互连; 集电极接触延伸层，其由与所述集电体层相同的导电类型的掺杂半导体材料形成，所述集电极接触延伸层与所述集电极层接触并从其一侧或下方延伸; 以及集电极触点互连，其设置在集电极接触延伸层的表面上，并且仅通过一个或多个绝缘层与所述发射极层分离。

83. 发明授权

US4957875A Vertical bipolar transistor 失效
标题翻译：垂直双极晶体管
公开(公告)号：US4957875A
公开(公告)日：1990-09-18
申请号：US226738
申请日：1988-08-01
申请人： Shah Akbar , Patricia L. Kroesen , Seiki Ogura , Nivo Rovedo
发明人： Shah Akbar , Patricia L. Kroesen , Seiki Ogura , Nivo Rovedo
IPC分类号： H01L29/73 , G03C3/00 , H01L21/331 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/737
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/1004 , H01L29/732 , Y10S148/009 , Y10S148/011
摘要： A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposeed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect disposed on a surface of the base contact extension layer and; a collector contact extension layer formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.

84. 发明授权

US4001612A Linear resistance element for LSI circuitry 失效
标题翻译： LSI电路的线性电阻元件
公开(公告)号：US4001612A
公开(公告)日：1977-01-04
申请号：US641469
申请日：1975-12-17
申请人： Takaaki Aoki , Paul Evrenidis , Ryo Igarashi , Seiki Ogura
发明人： Takaaki Aoki , Paul Evrenidis , Ryo Igarashi , Seiki Ogura
IPC分类号： H01L27/04 , H01L21/822 , H01L27/088 , H01L29/78 , H01L27/02 , H01L29/66
CPC分类号： H01L27/088 , H01L29/78
摘要： This invention features the use of two paralleled insulated gate depletion channel field effect transistors (FET) having their gates connected one to the source voltage and one to the drain voltage to provide a linear resistance element. The actual resistance value can be controlled by selecting design parameters and can be extended by using a plurality of such elements in series to provide greater resistances and/or higher voltage capabilities or in parallel to provide greater current capacity. The described resistor is used as a cost and space saving alternate to discrete resistor components and is particularly useful as a part of an integrated circuit in analog type devices.

85. 发明授权

US08139410B2 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US08139410B2
公开(公告)日：2012-03-20
申请号：US12802910
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

86. 发明授权

US08023326B2 Trap-charge non-volatile switch connector for programmable logic 有权
标题翻译：用于可编程逻辑的陷阱充电非易失性开关连接器
公开(公告)号：US08023326B2
公开(公告)日：2011-09-20
申请号：US12802894
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。输出由连接到字栅极下方的通道的扩散形成。两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

87. 发明授权

US07742336B2 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US07742336B2
公开(公告)日：2010-06-22
申请号：US11982172
申请日：2007-11-01
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

88. 发明申请

US20090200603A1 High density vertical structure nitride flash memory 有权
标题翻译：高密度垂直结构氮化物闪存
公开(公告)号：US20090200603A1
公开(公告)日：2009-08-13
申请号：US12378108
申请日：2009-02-11
申请人： Seiki Ogura , Tomoko Ogura Iwasaki , Nori Ogura
发明人： Seiki Ogura , Tomoko Ogura Iwasaki , Nori Ogura
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , G11C16/10 , H01L21/28282 , H01L27/108 , H01L27/10879 , H01L27/11563 , H01L27/11565 , H01L27/11568 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
摘要翻译：描述具有具有垂直和可能水平分量的存储器通道的存储器的电荷陷阱型。本发明包括用于高速和高可靠性非易失性存储器以及高密度非易失性存储器的同时空穴和电子注入操作的新操作方法。还描述了用于高密度存储器阵列和高速存储器阵列的阵列实现及其制造方法。

89. 发明申请

US20070047307A1 High speed operation method for twin MONOS metal bit array 有权
标题翻译：双MONOS金属钻头阵列的高速运行方式
公开(公告)号：US20070047307A1
公开(公告)日：2007-03-01
申请号：US11215418
申请日：2005-08-30
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.
摘要翻译：本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新颖操作方法。在本发明的第一实施例中，替代控制栅极被设置在相同的电压。在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。在两个实施例中，位线和字门被用于寻址选定的存储单元。

90. 发明申请

US20060203562A1 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US20060203562A1
公开(公告)日：2006-09-14
申请号：US11409247
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

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