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81. 发明申请

US20090148677A1 HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD 失效
标题翻译：高比例电镀金属特征及方法
公开(公告)号：US20090148677A1
公开(公告)日：2009-06-11
申请号：US11953359
申请日：2007-12-10
申请人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
发明人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
IPC分类号： C25D5/02 , B32B3/00
CPC分类号： C25D5/02 , Y10T428/24331 , Y10T428/24917
摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.
摘要翻译：公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料没有接缝和/或空隙。此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

82. 发明授权

US07544578B2 Structure and method for stochastic integrated circuit personalization 失效
标题翻译：随机集成电路个性化的结构与方法
公开(公告)号：US07544578B2
公开(公告)日：2009-06-09
申请号：US11619196
申请日：2007-01-03
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/20
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

83. 发明授权

US07531384B2 Enhanced interconnect structure 失效
标题翻译：增强的互连结构
公开(公告)号：US07531384B2
公开(公告)日：2009-05-12
申请号：US11548298
申请日：2006-10-11
申请人： Chih-Chao Yang , Mukta Ghate Farooq , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Mukta Ghate Farooq , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76843 , H01L21/76883 , H01L21/76885 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.
摘要翻译：本发明提供了一种在封盖层/电介质层/扩散阻挡界面处具有改进的机械强度的半导体互连结构。互连结构具有嵌入Cu封盖材料中的Cu扩散阻挡材料。阻挡层可以部分地嵌入盖层中或完全嵌入封盖层中。

84. 发明申请

US20090079077A1 INTERCONNECT STRUCTURE WITH A VIA GOUGING FEATURE ABSENT PROFILE DAMAGE TO THE INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME 有权
标题翻译：具有通过特征的互连结构与互连电介质的损伤及其制造方法
公开(公告)号：US20090079077A1
公开(公告)日：2009-03-26
申请号：US11858166
申请日：2007-09-20
申请人： Chih-Chao Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Keith Kwong Hon Wong
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76814 , H01L21/32134 , H01L21/76805 , H01L21/76835 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76867 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure including a gouging feature at the bottom of the via openings and a method of forming the same, which does not introduce either damages caused by Ar sputtering into the dielectric material that includes the via and line openings, nor plating voids into the structure are provided. The method includes the uses of at least one infusion process that forms an infused surface region within a conductive material of a lower interconnect level. The infused surface region has a different etch rate as compared with the conductive material and thus in a subsequent etching process, the infused surface region can be selectively removed forming a gouging feature within the structure.
摘要翻译：包括通孔开口底部的气流特征的互连结构及其形成方法，其不引入由Ar溅射引入到包括通孔和线路开口的电介质材料中的损伤，也不会将空隙电镀到结构中被提供。该方法包括使用至少一个在较低互连级别的导电材料内形成输注表面区域的输注过程。输入的表面区域与导电材料相比具有不同的蚀刻速率，因此在随后的蚀刻工艺中，可以选择性地去除输注的表面区域，从而在结构内形成气蚀特征。

85. 发明申请

US20090039512A1 ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE 审中-公开
标题翻译：电阻互连结构
公开(公告)号：US20090039512A1
公开(公告)日：2009-02-12
申请号：US11835678
申请日：2007-08-08
申请人： Haining S. Yang , Chih-Chao Yang , Keith Kwong Hon Wong
发明人： Haining S. Yang , Chih-Chao Yang , Keith Kwong Hon Wong
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883
摘要： A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls and the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a top surface of the dielectric layer and planarized to form a metal line in the line trench. The metal line is recessed by a recess etch below the top surface of the dielectric layer. A dielectric line cap or a metallic line cap is formed by deposition of a dielectric cap layer or a metallic cap layer, followed by planarization of the dielectric or metallic cap layer. The dielectric line cap or the metallic line cap applies a highly compressive stress on the underlying metal line, which increases electromigration resistance of the metal line.
摘要翻译：在可以包含层间绝缘材料的电介质层中形成线沟槽。金属衬垫形成在线沟槽的侧壁和底表面上。至少在电介质层的顶表面上，在导线沟槽的剩余部分内沉积导电金属，并平坦化以在线沟槽中形成金属线。金属线通过在电介质层的顶表面下方的凹陷蚀刻凹陷。介质线帽或金属线帽通过沉积介质盖层或金属覆盖层，然后平坦化介电层或金属覆盖层而形成。介质线帽或金属线帽在下面的金属线上施加高度压缩应力，这增加了金属线的电迁移阻力。

86. 发明申请

US20080290519A1 DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
公开(公告)号：US20080290519A1
公开(公告)日：2008-11-27
申请号：US12186932
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L23/48
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

87. 发明授权

US08642460B2 Semiconductor switching device and method of making the same 失效
标题翻译：半导体开关器件及其制造方法
公开(公告)号：US08642460B2
公开(公告)日：2014-02-04
申请号：US13155757
申请日：2011-06-08
申请人： Chih-Chao Yang , Stephen A Cohen , Baozhen Li
发明人： Chih-Chao Yang , Stephen A Cohen , Baozhen Li
IPC分类号： H01L21/44
CPC分类号： B82Y10/00 , H01L23/5252 , H01L29/413 , H01L2924/0002 , H01L2924/00
摘要： A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer, and a set of discrete islands of a low diffusion mobility metal between the two conductive features. The discrete islands of the low diffusion mobility metal may be either on the first top surface or embedded in the first dielectric layer. The electric conductivity across the two conductive features of the switching device increases when a prescribed voltage is applied to the two conductive features. A method of forming such a switching device is also provided.
摘要翻译：一种开关装置，包括具有第一顶表面的第一介电层，嵌入在第一介电层中的两个导电特征，每个导电特征具有与第一介电层的第一顶表面基本上共面的第二顶表面，以及一组在两个导电特征之间的低扩散迁移率金属的离散岛。低扩散迁移率金属的离散岛可以在第一顶表面上或嵌入在第一介电层中。当规定的电压施加到两个导电特征时，开关装置的两个导电特征的电导率增加。还提供了一种形成这种开关装置的方法。

88. 发明授权

US08421186B2 Electrically programmable metal fuse 有权
标题翻译：电子可编程金属保险丝
公开(公告)号：US08421186B2
公开(公告)日：2013-04-16
申请号：US13149108
申请日：2011-05-31
申请人： Baozhen Li , Chunyan E. Tian , Chih-Chao Yang
发明人： Baozhen Li , Chunyan E. Tian , Chih-Chao Yang
IPC分类号： H01L29/00 , H01L23/525 , H01H37/76
CPC分类号： H01L23/5256 , G11C17/16 , G11C29/785 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.
摘要翻译：金属电可编程保险丝（eFuse）包括在金属条的两端处具有与宽金属线部分相邻的金属线的具有宽度大于金属带宽度的宽度的金属带。条带宽度可以是光刻最小尺寸，并且金属条带的长度与条带宽度的比率大于5以在编程期间定位围绕金属条的中心的加热。加热的本地化减少了用于编程金属eFuse所需的电力。此外，在金属带的长于Blech长度的部分内的编程期间形成逐渐的温度梯度，使得金属的电迁移在金属带的中心部分逐渐发生。金属线部分提供与金属eFuse相同的水平，以物理阻挡编程期间产生的碎屑。

89. 发明申请

US20100314764A1 HYBRID METALLIC WIRE AND METHODS OF FABRICATING SAME 失效
标题翻译：混合金属线及其制造方法
公开(公告)号：US20100314764A1
公开(公告)日：2010-12-16
申请号：US12482777
申请日：2009-06-11
申请人： Chih-Chao Yang , Kaushik Chanda , Daniel Edelstein , Baozhen Li
发明人： Chih-Chao Yang , Kaushik Chanda , Daniel Edelstein , Baozhen Li
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76846 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.
摘要翻译：一种制造结构的结构和方法。该结构包括：介电层中的沟槽; 导电衬垫，导电芯导体和填充所述衬套和所述芯导体之间的空隙的导电填充材料。

90. 发明授权

US07692439B2 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US07692439B2
公开(公告)日：2010-04-06
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

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