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81. 发明授权

US08728897B2 Power sige heterojunction bipolar transistor (HBT) with improved drive current by strain compensation 有权
标题翻译：功率奇异异质结双极晶体管（HBT）通过应变补偿提高驱动电流
公开(公告)号：US08728897B2
公开(公告)日：2014-05-20
申请号：US13342797
申请日：2012-01-03
申请人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
发明人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
IPC分类号： H01L21/336
CPC分类号： H01L29/66242 , H01L21/76232 , H01L22/20 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/7371
摘要： A power SiGe heterojunction bipolor transistor (HBT) with improved drive current by strain compensation and methods of manufacture are provided. A method includes adding carbon in a continuous steady concentration in layers of a device including a subcollector layer, a collector layer, a base buffer layer, a base layer, and an emitter buffer layer.
摘要翻译：提供了通过应变补偿和制造方法提高驱动电流的功率SiGe异质结双色晶体管（HBT）。一种方法包括在包括子集电极层，集电极层，基极缓冲层，基极层和发射极缓冲层的器件的层中以连续稳定的浓度添加碳。

82. 发明申请

US20130334571A1 EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM 审中-公开
标题翻译：平滑和高应变的德国的外源生长
公开(公告)号：US20130334571A1
公开(公告)日：2013-12-19
申请号：US13526840
申请日：2012-06-19
申请人： Alexander Reznicek , Thomas N. Adam , Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana
发明人： Alexander Reznicek , Thomas N. Adam , Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L29/78 , H01L29/24 , H01L21/20
CPC分类号： H01L29/165 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L29/1054 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate.
摘要翻译：可以在约350℃的温度下，在磷化氢存在下将衬底暴露于锗前体，可直接在硅半导体衬底上生长的光滑的锗层。可以在有或没有SiGe种子层的情况下实现锗层形成。形成锗层的过程可以集成到标准CMOS处理中，以有效地形成体现薄的，高度应变的锗层的结构。这种结构可以实现处理灵活性。锗层还可以提供独特的物理性质，例如在光电子器件中，或者能够在硅衬底上形成III-V族材料层。

83. 发明授权

US08415253B2 Low-temperature in-situ removal of oxide from a silicon surface during CMOS epitaxial processing 失效
标题翻译：在CMOS外延处理期间低温从硅表面原位去除氧化物
公开(公告)号：US08415253B2
公开(公告)日：2013-04-09
申请号：US13075657
申请日：2011-03-30
申请人： Thomas N. Adam , Stephen W. Bedell , Alexander Reznicek , Devendra K. Sadana
发明人： Thomas N. Adam , Stephen W. Bedell , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/311
CPC分类号： H01L21/02046
摘要： Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.
摘要翻译：提供低温原位技术用于在CMOS外延处理期间从硅表面去除氧化物。通过在硅表面上沉积SiGe层，从具有硅表面的半导体晶片去除氧化物; 在低于700℃（以上，例如约450℃）的温度下，从硅表面蚀刻SiGe层; 并重复沉积和蚀刻步骤多次，直到污染物基本上从硅表面除去。在一个变型中，沉积层包括IV族半导体材料和/或其合金。

84. 发明申请

US20130040440A1 EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 审中-公开
公开(公告)号：US20130040440A1
公开(公告)日：2013-02-14
申请号：US13613003
申请日：2012-09-13
申请人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
发明人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
IPC分类号： H01L21/20
CPC分类号： H01L21/0237 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/02661
摘要： A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.

85. 发明授权

US08361889B2 Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator 有权
标题翻译：通过在绝缘体上半导体中加入和除去原子的绝缘体上的应变半导体
公开(公告)号：US08361889B2
公开(公告)日：2013-01-29
申请号：US12830626
申请日：2010-07-06
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L29/7833
摘要： A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.
摘要翻译：提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸，下层SOI层的平面晶格参数。在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸，下层SOI层的平面晶格参数。在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。

86. 发明申请

US20120112208A1 STRESSED TRANSISTOR WITH IMPROVED METASTABILITY 有权
标题翻译：具有改进的均匀性的应力晶体管
公开(公告)号：US20120112208A1
公开(公告)日：2012-05-10
申请号：US12942289
申请日：2010-11-09
申请人： THOMAS N. ADAM , Stephen W. Bedell , Abhishek Dube , Eric C.T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
发明人： THOMAS N. ADAM , Stephen W. Bedell , Abhishek Dube , Eric C.T. Harley , Judson R. Holt , Alexander Reznicek , Devendra K. Sadana , Dominic J. Schepis , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L29/772 , H01L29/24 , H01L21/336
CPC分类号： H01L29/78 , H01L21/28525 , H01L21/76805 , H01L21/76877 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
摘要翻译：在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

87. 发明授权

US08288217B2 Stressor in planar field effect transistor device 失效
标题翻译：应力平面场效应晶体管器件
公开(公告)号：US08288217B2
公开(公告)日：2012-10-16
申请号：US12945026
申请日：2010-11-12
申请人： Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Alexander Reznicek , Keith Kwong Hon Wong
发明人： Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Alexander Reznicek , Keith Kwong Hon Wong
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L29/1054 , H01L29/66477 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.
摘要翻译：场效应晶体管器件包括设置在衬底上的栅极堆叠部分和衬底中的沟道区域，其具有由栅极堆叠部分和衬底的硅区域部分地限定的深度，所述硅区域具有倾斜轮廓，使得沟道区域的远侧区域具有比沟道区域的中间区域更深的深度。

88. 发明申请

US20120205784A1 GROWING COMPRESSIVELY STRAINED SILICON DIRECTLY ON SILICON AT LOW TEMPERATURES 有权
标题翻译：在低温下直接生长含硅的压敏硅
公开(公告)号：US20120205784A1
公开(公告)日：2012-08-16
申请号：US13037944
申请日：2011-03-01
申请人： Stephen W. Bedell , Bahman Hekmatshoartabari , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L29/02 , H01L21/20
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262
摘要： Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient.
摘要翻译：使用氢将压缩应变硅在低温下直接外延生长到硅衬底上以设计应变水平。在这样的生长过程中氢稀释可以变化以提供应变梯度。

89. 发明申请

US20120156861A1 QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE 审中-公开
标题翻译：使用水解硅表面和界面结合氧化物的溶解度的偶氮硅Si-Si波形粘结
公开(公告)号：US20120156861A1
公开(公告)日：2012-06-21
申请号：US13405760
申请日：2012-02-27
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/302
CPC分类号： H01L21/187 , H01L21/76251
摘要： Methods for removing or reducing the thickness of a material layer remaining at Si-Si interfaces after silicon wafer bonding. The methods include an anneal which is performed at a temperature sufficient to dissolve oxide, yet not melt silicon.
摘要翻译：在硅晶片接合之后去除或减少残留在Si-Si界面处的材料层的厚度的方法。所述方法包括在足以溶解氧化物但不熔融硅的温度下进行的退火。

90. 发明申请

US20120037998A1 CMOS TRANSISTORS WITH STRESSED HIGH MOBILITY CHANNELS 有权
标题翻译：具有强力高移动通道的CMOS晶体管
公开(公告)号：US20120037998A1
公开(公告)日：2012-02-16
申请号：US12855738
申请日：2010-08-13
申请人： Stephen W. Bedell , Jee H. Kim , Siegfried L. Maurer , Alexander Reznicek , Devendra K. Sadana
发明人： Stephen W. Bedell , Jee H. Kim , Siegfried L. Maurer , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L27/092 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7843 , H01L29/7848
摘要： A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.
摘要翻译：形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域。在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成，使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

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