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81. 发明授权

US09030870B2 Threshold voltage compensation in a multilevel memory 有权
标题翻译：多电平存储器中的阈值电压补偿
公开(公告)号：US09030870B2
公开(公告)日：2015-05-12
申请号：US13219439
申请日：2011-08-26
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C11/34 , G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

82. 发明授权

US08879329B2 Program verify operation in a memory device 有权
标题翻译：在存储设备中进行程序验证操作
公开(公告)号：US08879329B2
公开(公告)日：2014-11-04
申请号：US12949876
申请日：2010-11-19
申请人： Violante Moschiano , Giovanni Santin , Michele Incarnati
发明人： Violante Moschiano , Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34 , G11C16/06 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/26
摘要： Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of each count value is compared to an indication of a target threshold voltage for the memory cell. When the at least a portion of the count value is equal to the indication of the target threshold voltage indication, sense circuitry is used to check if the memory cell has been activated by the voltage generated by the count. If the memory cell has been activated, an inhibit latch is set to inhibit further programming of the memory cell. If the memory cell has not been activated by the voltage, the memory cell is biased with another programming pulse.
摘要翻译：公开了用于程序验证，程序验证电路和存储器件的方法。用于程序验证的一种这样的方法包括为多个计数值生成斜坡电压。斜坡电压被施加到被程序验证的存储器单元的控制栅极。将每个计数值的至少一部分与存储器单元的目标阈值电压的指示进行比较。当计数值的至少一部分等于目标阈值电压指示的指示时，感测电路用于检查存储器单元是否已被计数产生的电压激活。如果存储单元已被激活，则设置禁止锁存器以禁止存储器单元的进一步编程。如果存储单元没有被电压激活，则存储单元被另一编程脉冲偏置。

83. 发明授权

US08630125B2 Memory cell sensing using a boost voltage 有权
标题翻译：使用升压电压进行存储单元感应
公开(公告)号：US08630125B2
公开(公告)日：2014-01-14
申请号：US13151456
申请日：2011-06-02
申请人： Violante Moschiano , Domenico Di Cicco , Andrea D'Alessandro
发明人： Violante Moschiano , Domenico Di Cicco , Andrea D'Alessandro
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3436
摘要： The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line.
摘要翻译：本公开包括包括使用升压电压的存储器单元感测的装置，方法和系统。一个或多个实施例包括预先充电和/或浮动与所选择的存储器单元相关联的数据线，升压预充电和/或浮置数据线，以及基于感测到的放电，确定所选择的存储器单元的状态提升数据线后的数据线。

84. 发明授权

US08553461B2 Method for kink compensation in a memory 有权
公开(公告)号：US08553461B2
公开(公告)日：2013-10-08
申请号：US13585389
申请日：2012-08-14
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.

85. 发明授权

US08400827B2 Non-volatile memory programming 有权
标题翻译：非易失性存储器编程
公开(公告)号：US08400827B2
公开(公告)日：2013-03-19
申请号：US12795202
申请日：2010-06-07
申请人： Violante Moschiano , Giovanni Santin
发明人： Violante Moschiano , Giovanni Santin
IPC分类号： G11C16/00
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described.
摘要翻译：一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。一种这样的方法包括基于处于擦除状态的存储器单元的阈值电压将不同的电压施加到与不同存储器单元相关联的数据线。描述包括附加存储器件和方法的其它实施例。

86. 发明授权

US08391061B2 Flash memory and associated methods 有权
标题翻译：闪存和相关方法
公开(公告)号：US08391061B2
公开(公告)日：2013-03-05
申请号：US12643610
申请日：2009-12-21
申请人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
发明人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译：在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。

87. 发明申请

US20130039138A1 METHODS FOR PROVIDING REDUNDANCY AND APPARATUSES 有权
标题翻译：提供冗余和装置的方法
公开(公告)号：US20130039138A1
公开(公告)日：2013-02-14
申请号：US13208502
申请日：2011-08-12
申请人： Violante Moschiano , Giovanni Santin , Maria L. Gallese , Luigi Pilolli
发明人： Violante Moschiano , Giovanni Santin , Maria L. Gallese , Luigi Pilolli
IPC分类号： G11C29/04
CPC分类号： G11C29/846 , G11C16/0483 , G11C29/76 , G11C29/82 , G11C2229/723
摘要： Methods for providing redundancy and apparatuses are disclosed. One such method for providing redundancy performs a mapping of data between an address of a memory determined to indicate a defective memory cell and an address of a redundant area of the memory, only after the data has been loaded into a buffer. The direction of the mapping is determined by the operation (e.g., programming or reading).
摘要翻译：公开了提供冗余和装置的方法。用于提供冗余的一种这样的方法仅在数据被加载到缓冲器之后才能执行确定为指示缺陷存储器单元的存储器的地址与存储器的冗余区域的地址之间的数据映射。映射的方向由操作（例如，编程或读取）确定。

88. 发明授权

US08243521B2 Method for kink compensation in a memory 有权
标题翻译：存储器中的扭结补偿方法
公开(公告)号：US08243521B2
公开(公告)日：2012-08-14
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译：本公开涉及存储器扭结补偿。一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。在施加顺序递增的编程脉冲数之后施加接种电压。在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

89. 发明申请

US20120127794A1 PROGRAM VERIFY OPERATION IN A MEMORY DEVICE 有权
标题翻译：存储器件中的程序验证操作
公开(公告)号：US20120127794A1
公开(公告)日：2012-05-24
申请号：US12949876
申请日：2010-11-19
申请人： Violante Moschiano , Giovanni Santin , Michele Incarnati
发明人： Violante Moschiano , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/26
摘要： Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of each count value is compared to an indication of a target threshold voltage for the memory cell. When the at least a portion of the count value is equal to the indication of the target threshold voltage indication, sense circuitry is used to check if the memory cell has been activated by the voltage generated by the count. If the memory cell has been activated, an inhibit latch is set to inhibit further programming of the memory cell. If the memory cell has not been activated by the voltage, the memory cell is biased with another programming pulse.
摘要翻译：公开了用于程序验证，程序验证电路和存储器件的方法。用于程序验证的一种这样的方法包括为多个计数值生成斜坡电压。斜坡电压被施加到被程序验证的存储器单元的控制栅极。将每个计数值的至少一部分与存储器单元的目标阈值电压的指示进行比较。当计数值的至少一部分等于目标阈值电压指示的指示时，感测电路用于检查存储器单元是否已被计数产生的电压激活。如果存储单元已被激活，则设置禁止锁存器以禁止存储器单元的进一步编程。如果存储单元没有被电压激活，则存储单元被另一编程脉冲偏置。

90. 发明申请

US20110299333A1 NON-VOLATILE MEMORY PROGRAMMING 有权
标题翻译：非易失性存储器编程
公开(公告)号：US20110299333A1
公开(公告)日：2011-12-08
申请号：US12795202
申请日：2010-06-07
申请人： Violante Moschiano , Giovanni Santin
发明人： Violante Moschiano , Giovanni Santin
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described.
摘要翻译：一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。一种这样的方法包括基于处于擦除状态的存储器单元的阈值电压将不同的电压施加到与不同存储器单元相关联的数据线。描述包括附加存储器件和方法的其它实施例。

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