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81. 发明申请

US20130217199A1 METHOD FOR FABRICATING RESISTIVE MEMORY DEVICE 审中-公开
标题翻译：用于制造电阻式存储器件的方法
公开(公告)号：US20130217199A1
公开(公告)日：2013-08-22
申请号：US13580952
申请日：2012-04-16
申请人： Ru Huang , Shenghu Tan , Lijie Zhang , Yue Pan , Yinglong Huang , Gengyu Yang , Yu Tang , Jun Mao , Yimao Cai
发明人： Ru Huang , Shenghu Tan , Lijie Zhang , Yue Pan , Yinglong Huang , Gengyu Yang , Yu Tang , Jun Mao , Yimao Cai
IPC分类号： H01L21/02
CPC分类号： H01L45/04 , G11C13/0007 , G11C2013/0073 , G11C2213/15 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： The present invention discloses a method for fabricating a resistive memory, including: fabricating a bottom electrode over a substrate; partially oxidizing a metal of the bottom electrode through dry-oxygen oxidation or wet-oxygen oxidation to form a metal oxide with a thickness of 3 nm to 50 nm as a resistive material layer; finally fabricating a top electrode over the resistive material layer. The present invention omits a step of depositing a resistive material layer in a conventional method, so as to greatly reduce the process complexity. Meanwhile, a self alignment between the resistive material layer and the bottom electrode can be realized. A full isolation between devices may be ensured so as to obviate the parasite effects occurred in the conventional process methods. Meanwhile, the actual area and designed area of the device are ensured to be consistent.
摘要翻译：本发明公开了一种制造电阻式存储器的方法，包括：在衬底上制造底电极; 通过干氧氧化或湿氧氧化部分氧化底部电极的金属，形成厚度为3nm至50nm的金属氧化物作为电阻材料层; 最后在电阻材料层上制造顶部电极。本发明省略了以常规方法沉积电阻材料层的步骤，从而大大降低了工艺的复杂性。同时，可以实现电阻材料层和底部电极之间的自对准。可以确保器件之间的完全隔离，以便消除常规工艺方法中发生的寄生效应。同时，确保设备的实际面积和设计面积一致。

82. 发明授权

US08513067B2 Fabrication method for surrounding gate silicon nanowire transistor with air as spacers 有权
标题翻译：围绕栅极硅纳米线晶体管的制造方法，其中空气为间隔物
公开(公告)号：US08513067B2
公开(公告)日：2013-08-20
申请号：US13266791
申请日：2011-07-15
申请人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
发明人： Ru Huang , Jing Zhuge , Jiewen Fan , Yujie Ai , Runsheng Wang , Xin Huang
IPC分类号： H01L21/84
CPC分类号： H01L29/66439 , B82Y10/00 , H01L29/775
摘要： The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.
摘要翻译：本发明公开了一种具有空气作为间隔物的周围栅极硅纳米线晶体管的制造方法。该方法包括：执行隔离和沉积相对于Si具有较高蚀刻选择比的材料A; 执行光刻以限定Fin硬掩模; 蚀刻材料A以形成Fin硬掩模; 进行源极和漏极植入; 执行光刻以限定沟道区和大的源极/漏极区; 形成Si Fin和大源/排水; 去除材料A的硬掩模; 形成纳米线; 蚀刻SiO 2以形成浮动的纳米线; 形成栅氧化层; 沉积多晶硅; 执行多晶硅注入; 执行退火以激活掺杂剂; 蚀刻多晶硅; 沉积SiN; 执行光刻以限定栅极图案; 蚀刻SiN和多晶硅以形成栅极图案; 分离门和源/排水管之间的空间填充空气之间; 沉积SiO 2以形成空气侧壁; 进行退火以使SiO 2层致密化; 使用后续过程来完成器件制造。本发明与CMOS工艺流程兼容。空气侧壁的引入可以有效降低器件的寄生电容，提高器件的瞬态响应，使其适用于具有高性能的逻辑电路。

83. 发明授权

US08507959B2 Combined-source MOS transistor with comb-shaped gate, and method for manufacturing the same 有权
标题翻译：具有梳形门的组合源MOS晶体管及其制造方法
公开(公告)号：US08507959B2
公开(公告)日：2013-08-13
申请号：US13318333
申请日：2011-04-01
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
IPC分类号： H01L29/76 , H01L21/00 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/66643 , H01L29/7391 , H01L29/7839
摘要： The present invention discloses a combined-source MOS transistor with a Schottky Barrier and a comb-shaped gate structure, and a method for manufacturing the same. The combined-source MOS transistor includes: a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, wherein a Schottky source region is connected to a side of the highly-doped source region which is far from a channel, one end of the control gate extends to the highly-doped source region, the extended gate region is an extension gate in a form of a comb-shaped and the original control gate region is a main gate; an active region covered by the extension gate is also a channel region, and is a substrate material; the highly-doped source region which is formed by highly doping is located on both sides of each comb finger of the extension gate; and a Schottky junction is formed at a location where the Schottky source region and the channel under the extension gate are located. As compared with an existing MOSFET, in the invention, a higher turn-on current, a lower leakage current and a steeper subthreshold slope may be obtained under the same process condition and the same active region size.
摘要翻译：本发明公开了一种具有肖特基势垒和梳状栅极结构的组合源MOS晶体管及其制造方法。组合源MOS晶体管包括：控制栅极电极层，栅极电介质层，半导体衬底，高掺杂源极区域和高掺杂漏极区域，其中肖特基源极区域连接到高度远离通道的掺杂源极区域，控制栅极的一端延伸到高掺杂源极区域，延伸栅极区域是梳状形式的延伸栅极，并且原始控制栅极区域是大门; 由延伸栅极覆盖的有源区域也是沟道区域，并且是衬底材料; 通过高掺杂形成的高掺杂源区位于延伸门的每个梳齿的两侧; 并且在肖特基源区域和延伸门下方的沟道所在的位置处形成肖特基结。与现有的MOSFET相比，在本发明中，在相同的工艺条件和相同的有源区域尺寸下可以获得较高的导通电流，较低的漏电流和更陡的亚阈值斜率。

84. 发明申请

US20130103351A1 Method for Predicting Reliable Lifetime of SOI Mosfet Device 有权
标题翻译：用于预测SOI Mosfet器件可靠寿命的方法
公开(公告)号：US20130103351A1
公开(公告)日：2013-04-25
申请号：US13504433
申请日：2011-11-30
申请人： Ru Huang , Dong Yang , Xia An , Xing Zhang
发明人： Ru Huang , Dong Yang , Xia An , Xing Zhang
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G01R31/287
摘要： Disclosed herein is a method for predicting a reliable lifetime of a SOI MOSFET device. The method comprises: measuring a relationship of a gate resistance of the SOI MOSFET device varying as a function of a temperature at different wafer temperatures; performing a lifetime accelerating test on the SOI MOSFET device at different wafer temperatures, so as to obtain a degenerating relationship of a parameter representing the lifetime of the device as a function of stress time, and obtain a lifetime in the presence of self-heating when the parameter degenerates to 10%; performing a self-heating correction on the measured lifetime of the device by using the measured self-heating temperature and an Arrhenius model, so as to obtain a lifetime without self-heating influence; performing a self-heating correction on a variation of the drain current caused by self-heating; performing a self-heating correction on an impact ionization rate caused by hot carriers; and predicting the lifetime of the SOI MOSFET device under a bias. The embodiment of the invention prevents the self-heating effect from affecting the SOI MOSFET device in a practical logic circuit or in an AC analog circuit, which leads to a more precise prediction result.
摘要翻译：这里公开了一种用于预测SOI MOSFET器件的可靠寿命的方法。该方法包括：测量SOI MOSFET器件的栅极电阻与不同晶片温度下温度变化的关系; 在不同晶片温度下对SOI MOSFET器件进行寿命加速测试，以获得表示器件寿命作为应力时间的函数的退化关系，并在存在自热的情况下获得寿命参数退化为10％; 通过使用测量的自热温度和Arrhenius模型对器件的测量寿命进行自加热校正，以获得没有自热影响的寿命; 对由自加热引起的漏极电流的变化进行自热校正; 对热载体产生的冲击电离率进行自热校正; 并且在偏压下预测SOI MOSFET器件的寿命。本发明的实施例防止了自发热效应影响实际逻辑电路或AC模拟电路中的SOI MOSFET器件，这导致更精确的预测结果。

85. 发明申请

US20130099300A1 Floating Gate Structure of Flash Memory Device and Method for Fabricating the Same 有权
标题翻译：闪存设备的浮动门结构及其制造方法
公开(公告)号：US20130099300A1
公开(公告)日：2013-04-25
申请号：US13498585
申请日：2011-11-30
申请人： Yimao Cai , Song Mei , Ru Huang
发明人： Yimao Cai , Song Mei , Ru Huang
IPC分类号： H01L29/788 , H01L21/283
CPC分类号： H01L21/28273
摘要： The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an I-shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.
摘要翻译：本发明公开了一种闪存器件的浮动栅极结构及其制造方法，涉及超大规模集成电路的制造技术中的非易失性存储器。在本发明中，通过在闪速存储器的标准处理中，即通过添加三个步骤的沉积，两个步骤的蚀刻和CMP的一个步骤来修改浮动栅极的制造，形成I形的浮动栅极。除了这些步骤之外，所有其他步骤与闪存过程的标准过程相同。通过本发明，可以有效地改善耦合比，并且可以降低相邻器件之间的串扰，而不增加额外的光掩模，并且几乎不增加工艺复杂性，这对于提高编程速度和可靠性非常重要。

86. 发明申请

US20130075701A1 PROGRAMMABLE ARRAY OF SILICON NANOWIRE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：硅纳米管场效应晶体管的可编程阵列及其制造方法
公开(公告)号：US20130075701A1
公开(公告)日：2013-03-28
申请号：US13503240
申请日：2011-11-18
申请人： Ru Huang , Jibin Zou , Runsheng Wang , Jiewen Fan , Changze Liu , Yangyuan Wang
发明人： Ru Huang , Jibin Zou , Runsheng Wang , Jiewen Fan , Changze Liu , Yangyuan Wang
IPC分类号： H01L29/66
CPC分类号： H01L29/66977 , B82Y10/00 , B82Y99/00 , H01L21/02603 , H01L21/823828 , H01L21/823885 , H01L27/092 , H01L29/0673 , H01L29/66439 , H01L29/775
摘要： The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.
摘要翻译：本发明公开了一种基于硅纳米线场效应晶体管的六边形可编程阵列及其制造方法。阵列包括纳米线器件，纳米线器件连接区域和栅极连接区域，其中纳米线器件具有圆筒形状，并且包括硅纳米线通道，栅极介电层和栅极区域，纳米线通道被包围通过所述栅极介电层，并且所述栅极介电层被所述栅极区域包围; 纳米线器件以六边形形式布置以形成编程单元，纳米线器件连接区域是三个纳米线器件的连接节点并且固定到硅支撑体。本发明可以实现互连的复杂控制逻辑，并且适用于具有高集成度和高速度的数字/模拟和混合信号电路。

87. 发明申请

US20120261740A1 FLASH MEMORY AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：闪存及其制造方法
公开(公告)号：US20120261740A1
公开(公告)日：2012-10-18
申请号：US13389720
申请日：2011-10-14
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Shenghu Tan
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Shenghu Tan
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7391 , H01L27/1203 , H01L29/788 , H01L29/8616
摘要： The present invention discloses a flash memory and a method for fabricating the same, and relates to the technical field of the semiconductor memory. The flash memory includes a buried oxygen layer on which a source terminal, a channel, and a drain terminal are disposed, wherein the channel is between the source terminal and the drain terminal, and a tunneling oxide layer, a polysilicon floating gate, a blocking oxide layer, and a polysilicon control gate are sequentially disposed on the channel, and a thin silicon nitride layer is disposed between the source terminal and the channel. The method includes: 1) performing a shallow trench isolation on a SOI silicon substrate to form an active region; 2) sequentially forming a tunneling oxide layer and a first polysilicon layer on the SOI silicon substrate to form a polysilicon floating gate, and forming a blocking oxide layer and a second polysilicon layer to form a polysilicon control gate; 3) etching the resultant structure to form a gate stack structure; 4) forming a drain terminal at one side of the gate stack structure, etching the silicon film at the other side of the gate stack structure, growing a thin silicon nitride layer, and then refilling the hole structure with silicon material, to form a source terminal. The method has the advantages of high programming efficiency, low power consumption, effectively preventing source-drain punchthrough effect.
摘要翻译：本发明公开了一种闪速存储器及其制造方法，涉及半导体存储器的技术领域。闪速存储器包括掩埋氧层，其上设置有源极端子，沟道和漏极端子，其中沟道位于源极端子和漏极端子之间，以及隧道氧化物层，多晶硅浮动栅极，阻塞层氧化物层和多晶硅控制栅极依次设置在沟道上，并且在源极端子和沟道之间设置有薄的氮化硅层。该方法包括：1）在SOI硅衬底上进行浅沟槽隔离以形成有源区; 2）在SOI硅衬底上依次形成隧道氧化物层和第一多晶硅层，以形成多晶硅浮栅，并形成阻挡氧化层和第二多晶硅层以形成多晶硅控制栅极; 3）蚀刻所得结构以形成栅叠层结构; 4）在栅极堆叠结构的一侧形成漏极端子，蚀刻栅极叠层结构的另一侧的硅膜，生长薄的氮化硅层，然后用硅材料再填充孔结构，以形成源极终奌站。该方法具有编程效率高，功耗低，有效防止源极漏极穿通效应的优点。

88. 发明申请

US20120223361A1 LOW-POWER CONSUMPTION TUNNELING FIELD-EFFECT TRANSISTOR WITH FINGER-SHAPED GATE STRUCTURE 审中-公开
标题翻译：具有手指形状结构的低功耗消耗隧道场效应晶体管
公开(公告)号：US20120223361A1
公开(公告)日：2012-09-06
申请号：US13378920
申请日：2011-05-19
申请人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
发明人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/42312 , H01L29/66356
摘要： The present invention discloses a low-power consumption tunnelling field-effect transistor (TFET). The TFET according to the invention includes a source, a drain and a control gate, wherein the control gate extends towards the source to form a finger-type control gate, which includes an extended gate region and an original control gate region, and an active region covered by the extended gate region is also an channel region and is made of the substrate material. The invention employs a finger-shaped gate structure, and the source region of the TFET surrounds the channel so that the on-state current of the device is improved. In comparison with the conventional planar TFET, a higher on-state current and a steeper subthreshold slope may be obtained under the same process conditions and with the same active region size.
摘要翻译：本发明公开了一种低功耗隧道场效应晶体管（TFET）。根据本发明的TFET包括源极，漏极和控制栅极，其中控制栅极朝向源极延伸以形成指状型控制栅极，其包括扩展栅极区域和原始控制栅极区域，以及主动由扩展栅极区域覆盖的区域也是沟道区域并且由衬底材料制成。本发明采用指形栅极结构，并且TFET的源极区域围绕沟道，使得器件的导通电流得以改善。与传统的平面TFET相比，可以在相同的工艺条件和相同的有源区域尺寸下获得更高的导通电流和更陡的亚阈值斜率。

89. 发明申请

US20120199808A1 HIGH VOLTAGE-RESISTANT LATERAL DOUBLE-DIFFUSED TRANSISTOR BASED ON NANOWIRE DEVICE 有权
标题翻译：基于纳米器件的高耐压侧向双通道晶体管
公开(公告)号：US20120199808A1
公开(公告)日：2012-08-09
申请号：US13381633
申请日：2011-04-01
申请人： Ru Huang , Jibin Zou , Runsheng Wang , Gengyu Yang , Yujie Al , Jiewen Fan
发明人： Ru Huang , Jibin Zou , Runsheng Wang , Gengyu Yang , Yujie Al , Jiewen Fan
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , H01L29/0649 , H01L29/0692 , H01L29/16 , H01L29/66439 , H01L29/775
摘要： The present invention provides a high voltage-resistant lateral double-diffused transistor based on a nanowire device, which relates to the field of microelectronics semiconductor devices. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s). The invention can improve the high voltage-resistant capability of a lateral double-diffused transistor based on a silicon nanowire MOS transistor.
摘要翻译：本发明提供了一种基于纳米线器件的高耐压横向双扩散晶体管，其涉及微电子半导体器件的领域。横向双扩散MOS晶体管包括沟道区，栅极电介质，栅极区，源极区，漏极区，源极延伸区和漏极端S形漂移区，其中沟道区具有侧向圆柱形硅纳米线结构，其上均匀地覆盖一层栅极电介质，栅极区在栅极电介质上，栅极区和栅极电介质完全围绕沟道区，源极延伸区位于源区和漏极端S形漂移区域位于漏极区域和沟道区域之间，排水端S形漂移区域的平面图为单个或多个S形结构的形式，并且相对介电常数为1-4的绝缘材料填充在S形结构内。本发明可以提高基于硅纳米线MOS晶体管的横向双扩散晶体管的耐高压能力。

90. 发明授权

US07652492B2 Integrated compound nano probe card 有权
标题翻译：综合复合纳米探针卡
公开(公告)号：US07652492B2
公开(公告)日：2010-01-26
申请号：US12071311
申请日：2008-02-20
申请人： Horng-Jee Wang , Ya-Ru Huang , Min-Chieh Chou
发明人： Horng-Jee Wang , Ya-Ru Huang , Min-Chieh Chou
IPC分类号： G01R31/02
CPC分类号： G01R1/06755 , B82Y10/00 , B82Y30/00 , G01R1/07314 , G01R3/00 , H01L2924/00013 , Y10S977/742 , H01L2224/29099
摘要： An integrated compound nano probe card is disclosed to include a substrate layer having a front side and a back side, and compound probe pins arranged in the substrate layer. Each compound probe pin has a bundle of aligned parallel nanotubes/nanorods and a bonding material bonded to the bundle of aligned parallel nanotubes/nanorods and filled in gaps in the nanotubes/nanorods. Each compound probe pin has a base end exposed on the back side of the substrate layer and a distal end spaced above the front side of the substrate layer.
摘要翻译：公开了一种集成化合物纳米探针卡，其包括具有前侧和背侧的基底层和布置在基底层中的复合探针。每个复合探针都具有一对排列的平行的纳米管和纳米棒，以及粘合到对齐的平行纳米管/纳米棒束上并且填充在纳米管/纳米棒中的间隙中的粘合材料。每个复合探针具有暴露在基底层的背面上的基端和在基底层的前侧间隔开的远端。

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