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81. 发明授权

US07519884B2 TAM controller for plural test access mechanisms 有权
标题翻译： TAM控制器用于多个测试访问机制
公开(公告)号：US07519884B2
公开(公告)日：2009-04-14
申请号：US11762893
申请日：2007-06-14
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318555 , G01R31/318563
摘要： A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
摘要翻译：提供了一种器件测试体系结构和接口，可以高效地测试器件内的嵌入式内核。测试架构与标准IEEE 1500核心测试包装器相连接，并从外部测试仪器向封装器提供高测试数据带宽。测试架构包括比较电路，允许比较要在设备内执行的测试响应数据。测试架构还包括用于存储测试响应比较结果的存储器。测试架构包括一个可编程测试控制器，通过从外部测试仪简单地向可编程测试控制器输入指令来允许各种测试控制操作。测试架构包括用于选择用于测试的核心的选择器电路。还公开了设备测试架构的附加特征和实施例。

82. 发明申请

US20090058448A1 PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS 有权
公开(公告)号：US20090058448A1
公开(公告)日：2009-03-05
申请号：US12265493
申请日：2008-11-05
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/27 , G01R31/02
CPC分类号： G01R31/2851 , G01R31/31715 , G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318563 , G01R31/31919
摘要： An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits (704). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.

83. 发明授权

US07491970B2 IC with comparator receiving expected and mask data from pads 有权
标题翻译： IC与比较器接收来自焊盘的预期和掩模数据
公开(公告)号：US07491970B2
公开(公告)日：2009-02-17
申请号：US11971561
申请日：2008-01-09
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58 , G01R31/26
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

84. 发明申请

US20080320351A1 LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS 有权
标题翻译：低功耗扫描和延迟测试方法和设备
公开(公告)号：US20080320351A1
公开(公告)日：2008-12-25
申请号：US12204267
申请日：2008-09-04
申请人： Lee D. Whetsel , Joel J. Graber
发明人： Lee D. Whetsel , Joel J. Graber
IPC分类号： G01R31/3177 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/31721 , G01R31/3177 , G01R31/318541 , G01R31/318547 , G01R31/318575 , G01R31/31858 , G01R31/318586
摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
摘要翻译：扫描和扫描BIST架构通常用于测试集成电路中的数字电路。本公开改进了低功率扫描和扫描BIST方法。该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

85. 发明授权

US07454677B2 Two boundary scan cell switches controlling input to output buffer 有权
标题翻译：两个边界扫描单元开关控制输入到输出缓冲器
公开(公告)号：US07454677B2
公开(公告)日：2008-11-18
申请号：US11745532
申请日：2007-05-08
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/31715 , G01R31/318541 , G01R31/318572
摘要： A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic circuit. The cell is placed in a test mode that disables normal operation of the logic circuit. The data scanned into the input memory circuit is transferred into the output memory circuit simultaneous with the placing the cell in the test mode. A transmission gate between the logic circuit and the output memory circuit and a transmission gate between the input memory circuit and the output memory circuit effect the changes between normal operation and test modes.
摘要翻译：处理初始化位于集成电路内逻辑电路边界的扫描单元的输出存储器电路的状态。数据被扫描到单元的输入存储器电路中，同时将单元维持在提供逻辑电路的正常操作的模式中。电池被置于禁止逻辑电路正常工作的测试模式。将扫描到输入存储器电路中的数据与将单元放置在测试模式中同时被传送到输出存储器电路。逻辑电路和输出存储电路之间的传输门和输入存储器电路与输出存储电路之间的传输门影响正常操作和测试模式之间的变化。

86. 发明申请

US20080276142A1 WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE 有权
标题翻译：使用2信号JTAG接口进行测距
公开(公告)号：US20080276142A1
公开(公告)日：2008-11-06
申请号：US12175655
申请日：2008-07-18
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
摘要翻译：晶片上晶片的测试是通过以下方式实现的：（1）向测试人员提供使用同时双向收发器电路外部传送JTAG测试信号的能力;（2）使用同时双向收发器电路在晶片上提供外部传送JTAG测试信号的能力，以及（3）提供连接测试器的双向收发器电路与晶片上所选择的组或晶片上的所有芯片之间的机制，用于通信JTAG信号。

87. 发明申请

US20080263419A1 REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY 有权
标题翻译：可拆卸和可更换的TAP域选择电路
公开(公告)号：US20080263419A1
公开(公告)日：2008-10-23
申请号：US12128384
申请日：2008-05-28
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3187 , G06F11/27
CPC分类号： G01R31/3177 , G01R31/28 , G01R31/318555 , G01R31/318572
摘要： Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.
摘要翻译：今天，许多IEEE 1149.1 Tap域的实例都包含在集成电路（IC）中。虽然所有TAP域可以在可在IC外部访问的扫描路径上串行连接，但通常优选具有访问Tap域或Tap域的选择性。因此，点选区域选择电路可能包含在IC中，并与Tap域一起放置在扫描路径中。理想情况下，如果需要修改在扫描路径中选择了哪个Tap域，则Tap域选择电路应该仅存在于扫描路径中。本公开描述了一种新颖的方法和装置，其允许在其已经用于选择分组域之后从扫描路径移除分接区域选择电路，并且当需要选择不同的分接区域时，将其替换回扫描路径。

88. 发明申请

US20080255791A1 INTERFACE TO FULL AND REDUCE PIN JTAG DEVICES 有权
标题翻译：接口完全并减少PIN JTAG器件
公开(公告)号：US20080255791A1
公开(公告)日：2008-10-16
申请号：US11874594
申请日：2007-10-18
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/00 , G06F19/00
CPC分类号： G01R31/31713 , G01R31/2815 , G01R31/2851 , G01R31/2884 , G01R31/3025 , G01R31/31703 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318558
摘要： The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
摘要翻译：本公开描述了用于访问基板上的设备的过程和设备。衬底可以仅包括全引脚JTAG器件（504），只有减少的引脚JTAG器件（506），或者是完全引脚和降低引脚JTAG器件的混合。使用在基板（408）和JTAG控制器（404）之间的单个接口（502）来实现访问。访问接口可以是有线接口或无线接口，并且可以用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

89. 发明申请

US20080250287A1 IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES 有权
标题翻译： IEEE 1149.1和P1500测试接口组合电路和过程
公开(公告)号：US20080250287A1
公开(公告)日：2008-10-09
申请号：US12140395
申请日：2008-06-17
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/31713 , G01R31/28 , G01R31/31724 , G01R31/31727 , G01R31/3177 , G01R31/318536 , G01R31/318594 , G06F1/12 , G06F13/287 , G06F13/4282 , H03K19/017509
摘要： In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.
摘要翻译：在第一实施例中，允许IEEE标准1149.1的TAP从IEEE标准P1500的WSP命令控制，使得通常由WSP控制的P1500架构被TAP控制。在第二实施例（1）中，基于TAP和WSP的架构被合并在一起，使得先前描述的架构元件的共享是可能的，并且（2）TAP和WSP测试接口被合并到单个优化的测试接口中，该接口是可操作的执行每个单独测试界面的所有操作。一种方法为TAP维护TAP指令寄存器的访问和控制提供了一个选择的数据寄存器，由TAP + ATC或离散的CaptureDR，UpdateDR，TransferDR，ShiftDR和ClockDR WSP访问和控制数据寄存器控制信号。

90. 发明授权

US07417450B2 Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit 有权
标题翻译：用双向TDI-TMS / TDO通道电路测试组合逻辑芯片
公开(公告)号：US07417450B2
公开(公告)日：2008-08-26
申请号：US11565979
申请日：2006-12-01
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/3177 , G01R31/2884 , G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318511 , G01R31/318533 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G01R31/318575 , G01R31/318577 , G01R31/318583 , G01R31/3187 , G06F1/3234
摘要： Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
摘要翻译：晶片上晶片的测试是通过以下方式实现的：（1）向测试人员提供使用同时双向收发器电路外部传送JTAG测试信号的能力;（2）使用同时双向收发器电路在晶片上提供外部传送JTAG测试信号的能力，以及（3）提供连接测试器的双向收发器电路与晶片上所选择的组或晶片上的所有芯片之间的机制，用于通信JTAG信号。

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