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81. 发明授权

US06468850B2 Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US06468850B2
公开(公告)日：2002-10-22
申请号：US09907097
申请日：2001-07-16
申请人： Junichi Karasawa , Kunio Watanabe , Takashi Kumagai
发明人： Junichi Karasawa , Kunio Watanabe , Takashi Kumagai
IPC分类号： H01L218238
CPC分类号： H01L27/105 , H01L27/1052
摘要： A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.
摘要翻译：半导体器件具有具有外围电路区域和存储单元区域的半导体衬底。在外围电路区域和存储单元区域之间形成具有第一导电性阱的边界区域。在外围电路区域形成第二导电性阱。外围电路区域中的阱与边界区域接触，但不与存储单元区域接触。在边界区域形成虚拟晶体管。虚拟晶体管被布置成与存储单元区域基本上相同的晶体管形成密度。

82. 发明授权

US06326107B1 Phase shift mask and process for manufacturing the same 有权
标题翻译：相移掩模及其制造方法
公开(公告)号：US06326107B1
公开(公告)日：2001-12-04
申请号：US09501572
申请日：2000-02-10
申请人： Kunio Watanabe
发明人： Kunio Watanabe
IPC分类号： G03F900
CPC分类号： G03F1/30 , G03F1/26
摘要： A phase-shifting mask includes a transparent substrate and a pattern formed of a translucent film on the transparent substrate. One of two regions of the substrate along both sidewalls of a trace of the pattern has a recess such that phases of exposure light passing through the two regions are 180° inverse to each other. The trace has different thicknesses on its sides adjacent to the two regions of the substrate so that phases of exposure light passing through the one region of the substrate and one side of the trace adjacent thereto are 180° inverse to each other and phases of exposure light passing through the other of the two regions of the substrate and the other side of the trace adjacent thereto are 180° inverse to each other.
摘要翻译：相移掩模包括透明基板和在透明基板上由半透明膜形成的图案。沿着图案迹线的两个侧壁的基板的两个区域中的一个具有凹部，使得穿过两个区域的曝光光的相位彼此相反180°。该迹线在其与衬底的两个区域相邻的侧面上具有不同的厚度，使得通过衬底的一个区域的曝光光的相位和与其相邻的迹线的一侧彼此相反180°并且曝光光的相位穿过衬底的两个区域中的另一个并且与其相邻的迹线的另一侧彼此相反180°。

83. 发明授权

US6093860A Method for producing perfluoro(n-pentane) 失效
标题翻译：制备全氟（正戊烷）的方法
公开(公告)号：US6093860A
公开(公告)日：2000-07-25
申请号：US337395
申请日：1999-06-22
申请人： Kunio Watanabe , Takashi Okazoe , Shin Tatematsu
发明人： Kunio Watanabe , Takashi Okazoe , Shin Tatematsu
IPC分类号： C07B61/00 , C07C17/04 , C07C19/08 , C07C17/00
CPC分类号： C07C17/04
摘要： A method for producing perfluoro(n-pentane), which comprises fluorinating perfluoro(2-pentene) by bringing the perfluoro(2-pentene) into contact with a fluorine gas in the presence of a solvent.
摘要翻译：一种全氟（正戊烷）的制造方法，其特征在于，在溶剂的存在下，使全氟（2-戊烯）与氟气接触，从而全氟（2-戊烯）氟化。

84. 发明授权

US5878097A Signal processing delay circuit 失效
标题翻译：信号处理延迟电路
公开(公告)号：US5878097A
公开(公告)日：1999-03-02
申请号：US865704
申请日：1997-05-30
申请人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
发明人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , H03H11/26 , H03H11/54 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/00 , H04L7/02 , H04L25/36 , H04L25/40
CPC分类号： H03L7/0805 , G11B20/10 , G11B20/1403 , H03K5/13 , H03L7/0812 , H03L7/0896 , H03L7/0995 , H04L7/02 , H04L7/0008 , H04L7/0041
摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
摘要翻译：制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。数据采集电路和数据写入电路各自包括模拟可变延迟电路。

85. 发明授权

US5675812A Peripheral equipment control device 失效
标题翻译：外围设备控制装置
公开(公告)号：US5675812A
公开(公告)日：1997-10-07
申请号：US540940
申请日：1995-10-11
申请人： Yukari Nagashige , Shoichi Miyazawa , Kunio Watanabe , Kouji Shida , Shinichi Kojima
发明人： Yukari Nagashige , Shoichi Miyazawa , Kunio Watanabe , Kouji Shida , Shinichi Kojima
IPC分类号： G06F1/32 , G06F13/10 , G06F15/78
CPC分类号： G06F1/3215 , G06F1/325 , G06F1/3268 , Y02B60/1246 , Y02B60/32
摘要： A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a sate in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep slate. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.
摘要翻译：插入在连接到主CPU的SCSI总线和诸如文件装置的外围设备之间的外围设备控制LSI。 LSI分为两大块。一个块识别通过SCSI总线发送的SCSI协议ID信号。另一个块产生一个信号，导致另一个块离开睡眠状态（低功耗模式）。在从主CPU等待命令的状态下，外围设备控制LSI允许包含ID识别部分的块保持活动，而另一个块保持在睡眠状态。在从主CPU接收到基于ID的选择（访问）信号时，LSI检测到访问操作的开始，并使其他块离开其休眠状态并变为活动状态。

86. 发明授权

US5450471A Mobile telephone unit which combines operation of a portable mobile telephone and a vehicle telephone 失效
标题翻译：组合便携式移动电话和车载电话的操作的移动电话单元
公开(公告)号：US5450471A
公开(公告)日：1995-09-12
申请号：US26684
申请日：1993-03-05
申请人： Tetsuya Hanawa , Akihide Nishiyama , Hideki Kurebayashi , Kunio Watanabe , Hideharu Suzuki , Isao Fudemoto
发明人： Tetsuya Hanawa , Akihide Nishiyama , Hideki Kurebayashi , Kunio Watanabe , Hideharu Suzuki , Isao Fudemoto
IPC分类号： H04B1/38 , H04W88/02 , H04Q7/32
CPC分类号： H04W88/02 , H04B1/38 , H04M1/6075
摘要： A mobile telephone unit which combines operation of a respective portable mobile telephone and a communication unit. The mobile telephone unit includes at least one portable telephone, a communication unit and a buffer unit. The communication unit includes an external connection terminal, a radio transmitter/receiver, a baseband processor, a communication controller and a handset. The buffer unit mounts at least one portable mobile telephone. The buffer unit includes a first buffer unit connector which is connectable to the external connection terminal of the communication unit, a second buffer connector which connects to a connector of a respective portable mobile telephone mounted on the buffer unit, an identifying mechanism for identifying the communication conditions of a respective portable mobile telephone mounted on the buffer unit, and a control signal transmitting mechanism for transmitting the communication conditions identified by the identifying mechanism to the communication controller of the communication unit. The communication controller is responsive to the transmitted communication conditions and adjusts the communication conditions of the communication unit so that a respective portable mobile telephone mounted on the buffer unit can communicate through the communication unit.
摘要翻译：一种组合各便携式移动电话和通信单元的操作的移动电话单元。移动电话单元包括至少一个便携式电话，通信单元和缓冲单元。通信单元包括外部连接终端，无线电发射机/接收机，基带处理器，通信控制器和手机。缓冲单元安装至少一个便携式移动电话。缓冲单元包括可连接到通信单元的外部连接端子的第一缓冲单元连接器，连接到安装在缓冲单元上的各个便携式移动电话的连接器的第二缓冲连接器，用于识别通信的识别机构安装在缓冲单元上的各个便携式移动电话的条件以及用于将由识别机构识别的通信条件发送到通信单元的通信控制器的控制信号发送机构。通信控制器响应所发送的通信条件并调整通信单元的通信条件，使得安装在缓冲单元上的各个便携式移动电话可以通过通信单元进行通信。

87. 发明授权

US5361364A Peripheral equipment control device 失效
标题翻译：外围设备控制装置
公开(公告)号：US5361364A
公开(公告)日：1994-11-01
申请号：US795697
申请日：1991-11-21
申请人： Yukari Nagashige , Shoichi Miyazawa , Kunio Watanabe , Kouji Shida , Shinichi Kojima
发明人： Yukari Nagashige , Shoichi Miyazawa , Kunio Watanabe , Kouji Shida , Shinichi Kojima
IPC分类号： G06F1/32 , G06F13/10 , G06F15/78
CPC分类号： G06F1/3215 , G06F1/325 , G06F1/3268 , Y02B60/1246 , Y02B60/32
摘要： A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a state in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep state. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.
摘要翻译：插入在连接到主CPU的SCSI总线和诸如文件装置的外围设备之间的外围设备控制LSI。 LSI分为两大块。一个块识别通过SCSI总线发送的SCSI协议ID信号。另一个块产生一个信号，导致另一个块离开睡眠状态（低功耗模式）。在从主CPU等待命令的状态下，外围设备控制LSI允许包含ID识别部分的块保持活动，而另一个块保持在睡眠状态。在从主CPU接收到基于ID的选择（访问）信号时，LSI检测到访问操作的开始，并使其他块离开其休眠状态并变为活动状态。

88. 发明授权

US5313588A SCSI controller and method for use on an information processing system 失效
标题翻译： SCSI控制器和用于信息处理系统的方法
公开(公告)号：US5313588A
公开(公告)日：1994-05-17
申请号：US921743
申请日：1992-07-30
申请人： Yukari Nagashige , Soichi Isono , Kouzi Shida , Kunio Watanabe
发明人： Yukari Nagashige , Soichi Isono , Kouzi Shida , Kunio Watanabe
IPC分类号： G06F13/12 , G06F15/02
CPC分类号： G06F13/124
摘要： An SCSI controller LSI comprising a CPU, command FIFO memories, a sequencer and a status register. The command FIFO memories store two commands issued consecutively by the CPU. The sequencer initially processes the first command, places a normal end code in the status register upon normal end of the command execution, and outputs a normal end interrupt set signal. At this point, a command indication bit for indicating the presence of an unexecuted bit is set. Then an AND gate inhibits the normal end interrupt set signal, and no interrupt signal is output. After the processing of the second command, the command indication bit is reset. This causes an interrupt signal to be output to the CPU. Thus when the first of the two consecutively issued commands ends normally, a normal end report to the CPU is omitted, and the interrupt signal for notifying the CPU of the normal end of command execution is inhibited.
摘要翻译：包括CPU，命令FIFO存储器，定序器和状态寄存器的SCSI控制器LSI。命令FIFO存储器存储由CPU连续发出的两个命令。顺控程序最初处理第一个命令，在命令执行正常结束时将状态寄存器中的正常结束代码置入正常结束中断设置信号。此时，设置用于指示未执行位的存在的命令指示位。然后与门禁止正常结束中断设置信号，并且不输出中断信号。处理第二个命令后，命令指示位被复位。这将导致中断信号输出到CPU。因此，当两个连续发出的命令中的第一个正常结束时，省略对CPU的正常结束报告，并且禁止用于通知CPU正常结束命令执行的中断信号。

89. 发明授权

US5240424A Electrical connector 失效
标题翻译：电连接器
公开(公告)号：US5240424A
公开(公告)日：1993-08-31
申请号：US925205
申请日：1992-08-06
申请人： Kazuhiro Honma , Kunio Watanabe , Takeshi Morita , Shingo Nanao
发明人： Kazuhiro Honma , Kunio Watanabe , Takeshi Morita , Shingo Nanao
IPC分类号： H01R13/623 , H01R13/639
CPC分类号： H01R13/639 , H01R13/623
摘要： An electrical connector includes a plug connector having a plug shell formed with a flange and a receptacle connector having a receptacle shell provided on its outer circumference with a fitting device. The electrical connector further includes a coupling ring surrounding the plug shell and rotatable and holding the flange of the plug shell. The coupling ring has on its inner circumference a fitting device fitted with the first mentioned fitting device and a flange urging portion for urging the flange. The electrical connector includes at least one wave-shaped annular spring interposed between the flange and the flange urging portion and rotatable together with the coupling ring. The wave-shaped annular ring and the flange are formed in their opposed surfaces with at least one protrusion and at least one recess, respectively, which are detachably fitted with each other, thereby forming a click lock device for causing the protrusion to fall into the recesses to produce click sound when the plug connector and the receptacle connector have been fitted.In an alternate embodiment, the electrical connector has some contacts connected to earth circuits which comprise earth lugs. The connector has a cylindrical shell, an insulator arranged in the cylindrical shell, and at least one contact detachably inserted in a piercing aperture formed in the insulator and connected to an electrical wire. The earth lug includes a first contacting portion contacting the cylindrical shell and a second contacting portion positioned in the piercing aperture and contacting the contact.
摘要翻译：电连接器包括具有形成有凸缘的插头壳和插座连接器的插头连接器，插座连接器具有在其外圆周上设置有插入装置的插座壳体。电连接器还包括围绕插头外壳并可旋转并保持插头外壳的凸缘的联接环。联接环在其内周上具有装配有第一所述装配装置的装配装置和用于推动凸缘的凸缘推动部分。电连接器包括至少一个波形环形弹簧，其插入在凸缘和凸缘推动部分之间并与联接环一起旋转。波形环形环和凸缘在其相对表面上分别形成有至少一个突起和至少一个凹部，该凹部彼此可拆卸地配合，从而形成用于使突起落入当安装插头连接器和插座连接器时，产生点击声的凹槽。在替代实施例中，电连接器具有连接到包括接地片的接地电路的一些触点。连接器具有圆柱形壳体，布置在圆柱形壳体中的绝缘体，以及可拆卸地插入形成在绝缘体中并连接到电线的穿孔中的至少一个触点。接地片包括接触圆柱形壳体的第一接触部分和位于穿孔中并接触接触件的第二接触部分。

90. 发明授权

US5085712A Iron/copper/chromium alloy material for high-strength lead frame or pin grid array 失效
标题翻译：用于高强度引线框架或引脚网格阵列的铁/铜/铬合金材料
公开(公告)号：US5085712A
公开(公告)日：1992-02-04
申请号：US527710
申请日：1990-05-23
申请人： Kunio Watanabe , Satoshi Nishimura , Kunishige Kaneko
发明人： Kunio Watanabe , Satoshi Nishimura , Kunishige Kaneko
IPC分类号： C22C9/00 , C22C38/20 , H01L21/48 , H01L23/495
CPC分类号： C22C38/20 , C22C9/00 , H01L21/4821 , H01L23/49579 , H01L2924/0002
摘要： An iron/copper/chromium alloy material for a high-strength lead frame or pin grid array, which comprises 20 to 90% by weight of Cu and 2.5 to 12% by weight of Cr, with the balance being mainly iron, and which has an average grain size number of at least 10 in each of the iron/chromium phase and the copper phase, is prepared by continuous casting, cold-working, and aging.

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