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81. 发明授权

US09177644B2 Low-voltage fast-write PMOS NVSRAM cell 有权
标题翻译：低压快写PMOS NVSRAM单元
公开(公告)号：US09177644B2
公开(公告)日：2015-11-03
申请号：US13965031
申请日：2013-08-12
申请人： Hsing-Ya Tsao , Peter Wung Lee
发明人： Hsing-Ya Tsao , Peter Wung Lee
IPC分类号： G11C14/00 , G11C16/04 , G11C16/16
CPC分类号： G11C14/0063 , G11C14/00 , G11C16/04 , G11C16/0433 , G11C16/16
摘要： This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM's PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.
摘要翻译：本发明公开了一种低电压快写12T或14T PMOS NVSRAM单元结构，其包括6T LV SRAM单元和一对两个3T或4T HV PMOS闪存串。由于PMOS和NMOS闪存单元的反向阈值电压分辨率，该PMOS NVSRAM单元在数据写入操作期间具有超过NMOS NVSRAM单元在SRAM和闪存对之间具有相同数据极性的优势。此外，该PMOS NVSRAM的PMOS闪存单元使用与NMOS NVSRAM类似的低电流FN隧穿方案，因此快速数据编程和擦除可以同时实现高达100 Mb的大密度。因此，在上电期间闪存数据加载到SRAM单元期间，具有1.2V VDD的NVSRAM的低功耗电压操作可以轻松设计，无需将FSL线耦合到任何VDD电平。

82. 发明申请

US20130182509A1 NEW 1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN 有权
标题翻译：新的1T1b和2T2b闪存的基于数据的EEPROM设计
公开(公告)号：US20130182509A1
公开(公告)日：2013-07-18
申请号：US13734777
申请日：2013-01-04
申请人： Peter Wung Lee , Hsing-Ya Tsao
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C16/34 , G11C16/14 , G11C16/06
CPC分类号： G11C16/14 , G11C16/0425 , G11C16/0458 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2216/14
摘要： An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.
摘要翻译：提供了一个单晶体管一位（1T1b）基于闪存的EEPROM单元，以及改进的键操作方案，包括施加负字线电压和降低的位线电压用于执行擦除操作，这大大降低了高压应力每个单元用于增强编程/擦除周期，同时减小单元大小。由1T1b闪存的EEPROM单元制成的阵列可以在每个程序周期的半页或全页分割编程和预充电周期下进行操作。在单元阵列中利用由Vdd器件制成的PGM缓冲器进一步节省了硅面积。另外，公开了从1T1b单元得到的双晶体管二位二位（2T2b）EEPROM单元，其额外的单元尺寸减小，但是编程和擦除操作与1T1b单元的操作相同，有利于没有过程变化，大大增强了存储密度，卓越的程序/擦除耐久循环，以及在高温环境下运行的能力。

83. 发明授权

US08345481B2 NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array 失效
标题翻译：基于NAND的NMOS NOR闪存单元，基于NAND的NMOS NOR闪存阵列，以及形成基于NAND的NMOS NOR闪存阵列的方法
公开(公告)号：US08345481B2
公开(公告)日：2013-01-01
申请号：US13317678
申请日：2011-10-25
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C2211/5641 , H01L27/11519 , H01L27/11521 , H01L27/11524 , Y10T29/41
摘要： A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
摘要翻译： NOR闪存非易失性存储器或可重构逻辑器件具有NOR闪存非易失性存储器电路阵列，其包括串联连接在NAND串中的电荷保持晶体管，使得至少一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过当电荷保持晶体管未被选择用于读取时的电荷保持晶体管。最上面的电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且最下面的电荷保持晶体管的源极连接到源极线并且平行于位线。电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

84. 发明授权

US08274829B2 Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS 失效
标题翻译：行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面，扇区和芯片单元中的擦除
公开(公告)号：US08274829B2
公开(公告)日：2012-09-25
申请号：US12455936
申请日：2009-06-09
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/34 , G11C11/4193
CPC分类号： G11C8/12 , G11C16/0416 , G11C16/08 , G11C16/12 , G11C16/16
摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.
摘要翻译：用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障。该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元，以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

85. 发明申请

US20110170357A1 NONVOLATILE MEMORY WITH A UNIFIED CELL STRUCTURE 有权
标题翻译：具有统一细胞结构的非易失性存储器
公开(公告)号：US20110170357A1
公开(公告)日：2011-07-14
申请号：US13072281
申请日：2011-03-25
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

86. 发明授权

US07289366B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07289366B2
公开(公告)日：2007-10-30
申请号：US11376076
申请日：2006-03-15
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

87. 发明申请

US20070076480A1 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
公开(公告)号：US20070076480A1
公开(公告)日：2007-04-05
申请号：US11633326
申请日：2006-12-04
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

88. 发明申请

US20060176739A1 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US20060176739A1
公开(公告)日：2006-08-10
申请号：US11391662
申请日：2006-03-28
申请人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

89. 发明授权

US06850438B2 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
公开(公告)号：US06850438B2
公开(公告)日：2005-02-01
申请号：US10351179
申请日：2003-01-24
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma
IPC分类号： G11C16/04 , G11C16/14 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2216/18 , G11C2216/22 , H01L27/11521 , H01L27/11524
摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

90. 发明授权

US06788612B2 Flash memory array structure suitable for multiple simultaneous operations 有权
公开(公告)号：US06788612B2
公开(公告)日：2004-09-07
申请号：US10423559
申请日：2003-04-25
申请人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
发明人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
IPC分类号： G11C800
CPC分类号： G11C16/10 , G11C7/18 , G11C8/12 , G11C2216/22
摘要： In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

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