专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US08060755B2 Apparatus and method for providing user-generated key schedule in a microprocessor cryptographic engine 有权
标题翻译：在微处理器加密引擎中提供用户生成的密钥调度的装置和方法
公开(公告)号：US08060755B2
公开(公告)日：2011-11-15
申请号：US10800983
申请日：2004-03-15
申请人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
发明人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
IPC分类号： G06F12/14 , G06F9/30 , H04L9/00 , H04L9/32 , H04K1/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125 , H04L2209/24
摘要： An apparatus and method for performing cryptographic operations within microprocessor. The apparatus includes an instruction register having a cryptographic instruction disposed therein, a keygen unit, and an execution unit. The cryptographic instruction is received by a microprocessor as part of an instruction flow executing on the microprocessor. The cryptographic instruction prescribes one of the cryptographic operations, and also prescribes that a user-generated key schedule be employed when executing the one of the cryptographic operations. The keygen unit is operatively coupled to the instruction register. The keygen unit directs the microprocessor to load the user-generated key schedule. The execution unit is operatively coupled to the keygen unit. The execution unit employs the user-generated key schedule to execute the one of the cryptographic operations. The execution unit includes a cryptography unit.
摘要翻译：一种用于在微处理器内执行加密操作的装置和方法。该装置包括其中设置有密码指令的指令寄存器，密钥单元和执行单元。加密指令由微处理器接收，作为在微处理器上执行的指令流的一部分。密码指令规定了一个加密操作，并且还规定了当执行一个加密操作时采用用户生成的密钥调度。密钥单元可操作地耦合到指令寄存器。 keygen单元指示微处理器加载用户生成的密钥计划。执行单元可操作地耦合到密钥发生单元。执行单元使用用户生成的密钥调度来执行密码操作之一。执行单元包括密码单元。

82. 发明申请

US20110202796A1 MICROPROCESSOR WITH SYSTEM-ROBUST SELF-RESET CAPABILITY 有权
标题翻译：具有系统稳定自复位能力的微处理器
公开(公告)号：US20110202796A1
公开(公告)日：2011-08-18
申请号：US12944269
申请日：2010-11-11
申请人： G. Glenn Henry , Darius D. Gaskins , Jason Chen
发明人： G. Glenn Henry , Darius D. Gaskins , Jason Chen
IPC分类号： G06F11/00 , G06F13/28 , G06F13/24
CPC分类号： G06F11/3648
摘要： A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.
摘要翻译：微处理器包括总线接口单元，该总线接口单元将微处理器连接到总线，总线包括一个信号，当被断言时，它指示所有总线代理人不要发起总线事务。微代码使得总线接口单元响应于检测到事件而声明信号并复位微处理器，但不会重置总线接口单元的断言总线上的信号的部分。复位后，微码使总线接口单元解除总线上的信号。此外，微代码设置一个标志，并在复位本身之前将微处理器状态保存到存储器中，但不会将中断控制器复位。复位后，微码从存储器重新加载微处理器的状态。然而，如果微码确定标志被设置，它将放弃重新加载中断控制器的状态。

83. 发明申请

US20110142229A1 APPARATUS AND METHOD FOR PERFORMING TRANSPARENT HASH FUNCTIONS 有权
标题翻译：用于执行透明散列函数的装置和方法
公开(公告)号：US20110142229A1
公开(公告)日：2011-06-16
申请号：US12977809
申请日：2010-12-23
申请人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
IPC分类号： H04L9/28
CPC分类号： H04L9/3239 , G06F9/30007 , G06F9/30065 , G06F9/30185 , G06F9/3895 , G06F21/64 , G06F21/72 , H04L9/0643 , H04L2209/125 , H04L2209/60
摘要： A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit, executing the one of the hash operations. The executing includes indicating whether the one of the hash operations has been interrupted by an interrupting event; first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.
摘要翻译：一种用于执行散列操作的方法，包括：接收规定所述散列操作之一和多个散列算法之一的哈希指令; 将所述散列指令转换成第一多个微指令和第二多个微指令; 并且经由哈希单元执行所述散列操作之一。所述执行包括指示所述散列操作中的一个是否已被中断事件中断; 首先在所述散列单元内执行所述第一多个微指令以产生输出数据; 第二执行x86整数单元内的第二多个微指令，与第一次执行一起执行以测试标志寄存器中的位，更新文本指针寄存器，以及在执行散列操作期间处理中断; 以及在允许待决中断进行之前将相应的中间散列值存储到存储器。

84. 发明授权

US07917568B2 X87 fused multiply-add instruction 有权
标题翻译： X87融合乘法指令
公开(公告)号：US07917568B2
公开(公告)日：2011-03-29
申请号：US11781754
申请日：2007-07-23
申请人： G. Glenn Henry , Timothy A. Elliott , Terry Parks
发明人： G. Glenn Henry , Timothy A. Elliott , Terry Parks
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/78 , G06F9/30014 , G06F9/30145 , G06F9/30163
摘要： An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.
摘要翻译：公开了x86架构微处理器的指令集中的x87融合乘法（FMA）指令。 FMA指令将两个因子操作数隐含地指定为x87 FPU寄存器堆栈的前两个操作数，并将第三个加数操作数明确指定为第三个x87 FPU寄存器堆栈寄存器。微处理器乘以前两个操作数，并将产品添加到第三个操作数以生成结果。结果存储在第三个寄存器中，前两个操作数从堆栈中弹出。在替代实施例中，第三操作数也被隐含地指定为存储在堆栈寄存器顶部下面的两个寄存器的寄存器中; 结果也存储在其中。指令操作码值在x87操作码范围内。

85. 发明申请

US20110060943A1 APPARATUS AND METHOD FOR DETECTION AND CORRECTION OF DENORMAL SPECULATIVE FLOATING POINT OPERAND 有权
标题翻译：用于检测和校正非线性浮动点操作的装置和方法
公开(公告)号：US20110060943A1
公开(公告)日：2011-03-10
申请号：US12793821
申请日：2010-06-04
申请人： G. Glenn Henry , Gerard M. Col , Timothy A. Elliott , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Timothy A. Elliott , Rodney E. Hooker , Terry Parks
IPC分类号： G06F11/14
CPC分类号： G06F9/3865 , G06F9/3001 , G06F9/30025
摘要： A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.
摘要翻译：微处理器包括被配置为接收其指令和操作数并执行指令的多个执行单元。指令调度器向执行单元发出指令并选择指令操作数的源。执行单元中的至少一个检测其中一个指令的操作数之一是反正态操作数，响应于检测到该反正态操作数而产生指示需要重播的指示，并将该反正态操作数提供给指令调度器对正反操作数进行检测的响应，而不是对正常操作数进行归一化。指令调度器响应于该指示来对归一化操作数进行归一化，并且当指令被重放时，使归一化操作数而不是反正态操作数提供给执行单元。

86. 发明申请

US20110035617A1 USER-INITIATABLE METHOD FOR DETECTING RE-GROWN FUSES WITHIN A MICROPROCESSOR 有权
标题翻译：用于在微处理器中检测再熔融熔融物的用户可触发的方法
公开(公告)号：US20110035617A1
公开(公告)日：2011-02-10
申请号：US12719291
申请日：2010-03-08
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F11/07
CPC分类号： G06F11/10 , G06F11/2236
摘要： A microprocessor includes a first plurality of fuses, selectively blown with a predetermined value for provision to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, selectively blown with error detection information used to detect an error in the first plurality of fuses such that a blown fuse of the microprocessor returned a non-blown binary value. In response to a user program instruction, the microprocessor is configured to determine whether there is an error in the first plurality of fuses such that a blown fuse returned a non-blown binary value using the error detection information from the second plurality of fuses.
摘要翻译：微处理器包括第一组多个保险丝，其被选择性地以预定值吹送，以供给微处理器的电路以控制微处理器的操作。微处理器还包括第二多个保险丝，其选择性地吹制有用于检测第一多个保险丝中的错误的错误检测信息，使得微处理器的保险丝熔断器返回非发送的二进制值。响应于用户程序指令，微处理器被配置为确定在第一多个保险丝中是否存在错误，使得熔丝熔丝使用来自第二多个保险丝的错误检测信息返回未熔二进制值。

87. 发明申请

US20110035616A1 DETECTION OF UNCORRECTABLE RE-GROWN FUSES IN A MICROPROCESSOR 有权
标题翻译：在微处理器中检测不正确的再熔融熔融物
公开(公告)号：US20110035616A1
公开(公告)日：2011-02-10
申请号：US12719260
申请日：2010-03-08
申请人： G. Glenn Henry , Darius D. Gaskins , Stephan Gaskins
发明人： G. Glenn Henry , Darius D. Gaskins , Stephan Gaskins
IPC分类号： G06F9/30 , G06F11/07
CPC分类号： G06F11/10 , G06F11/2236
摘要： A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the first plurality of fuses to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, blown with the predetermined number of the first plurality of fuses that are blown. In response to being reset, the microprocessor is configured to: read the first plurality of fuses and count a number of them that are blown; read the predetermined number from the second plurality of fuses; compare the counted number with the predetermined number read from the second plurality of fuses; and prevent itself from fetching and executing user program instructions if the number counted from reading the first plurality of fuses does not equal the predetermined number read from the second plurality of fuses.
摘要翻译：微处理器包括第一组多个保险丝，预定数量的保险丝被选择性地吹制。控制值从第一组多个保险丝提供给微处理器的电路以控制微处理器的操作。微处理器还包括第二组多个保险丝，其与预定数量的第一组熔断器熔断一起。响应于复位，微处理器被配置为：读取第一组多个保险丝并对其中的数量进行计数; 从第二组保险丝读出预定数量; 将所计数的数量与从所述第二多个保险丝读取的预定数量进行比较; 并且如果从读取第一多个保险丝计数的数量不等于从第二多个保险丝读取的预定数量，则防止其取出并执行用户程序指令。

88. 发明授权

US07849120B2 Microprocessor with random number generator and instruction for storing random data 有权
标题翻译：具有随机数发生器的微处理器和用于存储随机数据的指令
公开(公告)号：US07849120B2
公开(公告)日：2010-12-07
申请号：US11616039
申请日：2006-12-26
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F7/58
CPC分类号： G06F7/58 , G06F9/30003 , G06F9/3004 , G06F9/30087 , G06F11/27
摘要： A microprocessor includes a random number generator circuit (RNG) within its instruction set architecture (ISA). An RNG buffer accumulates zero or more bytes of random data generated by the RNG. An RNG counter maintains a count of the accumulated random data bytes. An instruction translator translates instructions of the ISA. The ISA includes a distinct instruction that instructs the microprocessor to write the bytes from the buffer to a first user-visible register of the microprocessor and to load the count from the counter to a second user-visible register of the microprocessor. The count is unspecified by the instruction and may be between zero or more. In another embodiment, the instruction instructs the microprocessor to store a number of random data bytes specified from the buffer to a destination specified by the instruction, wherein the specified number may be greater than the maximum amount of bytes the buffer can hold.
摘要翻译：微处理器在其指令集架构（ISA）内包括一个随机数发生器电路（RNG）。 RNG缓冲区累积由RNG生成的零个或多个字节的随机数据。 RNG计数器维护累加随机数据字节的计数。指令翻译器翻译ISA的指令。 ISA包括指示微处理器将字节从缓冲器写入微处理器的第一用户可见寄存器的独特指令，并将计数器的计数加载到微处理器的第二用户可见寄存器。计数未由指令指定，可能在零或更多之间。在另一个实施例中，指令指示微处理器将从缓冲器指定的多个随机数据字节存储到由指令指定的目的地，其中指定的数量可以大于缓冲器可以容纳的最大字节量。

89. 发明授权

US07827390B2 Microprocessor with private microcode RAM 有权
标题翻译：具有专用微码RAM的微处理器
公开(公告)号：US07827390B2
公开(公告)日：2010-11-02
申请号：US12034503
申请日：2008-02-20
申请人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/312
CPC分类号： G06F9/3824 , G06F9/26 , G06F9/30043 , G06F9/30101 , G06F9/30112 , G06F9/30123 , G06F9/30138 , G06F9/30174 , G06F9/3826
摘要： A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR.
摘要翻译：微处理器包括专用RAM（PRAM），用于微码，这是非用户可访问的，并且在其自身与系统存储器地址空间不同的地址空间内。 PRAM比微处理器宏构架的用户可访问的寄存器更密集和更慢，从而使其能够为微码提供显着更多的存储。微指令集包括用于将来自PRAM的数据加载到用户可访问寄存器中的微指令，以及用于将来自用户可访问寄存器的数据存储到PRAM的微指令。微代码还可以使用两个微指令来加载/存储在微架构的PRAM和非用户可访问的寄存器之间。 PRAM使用的示例包括：计算临时存储区域; 存储x86 VMX VMCS以响应VMREAD和VMWRITE宏指令; 实例化非用户可访问的存储，如x86 SMBASE寄存器; 以及容忍PRAM的附加访问延迟（例如IA32_SYSENTER_CS MSR）的x86 MSR的实例化。

90. 发明申请

US20100229062A1 DETECTION AND CORRECTION OF FUSE RE-GROWTH IN A MICROPROCESSOR 有权
标题翻译：微处理器中保险丝再生长的检测和校正
公开(公告)号：US20100229062A1
公开(公告)日：2010-09-09
申请号：US12609207
申请日：2009-10-30
申请人： G. Glenn Henry , Charles John Holthaus , Terry Parks
发明人： G. Glenn Henry , Charles John Holthaus , Terry Parks
IPC分类号： G06F11/07 , G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G11C17/18 , G06F11/1048 , G11C2029/0411
摘要： A microprocessor includes control hardware that receives and stores control values and provides the control values to circuits of the microprocessor for controlling operation of the microprocessor. The microprocessor also includes a first plurality of fuses selectively blown collectively with a predetermined value, and a second plurality of fuses selectively blown collectively with an error correction value computed from the predetermined value collectively blown into the first plurality of fuses. In response to being reset, the microprocessor reads the first and second plurality of fuses, detects an error in the value read from the first plurality of fuses using the value read from the second plurality of fuses, corrects the value read from the first plurality of fuses back to the predetermined value using the value read from the second plurality of fuses, and uses the corrected predetermined value to write the control values into the control hardware.
摘要翻译：微处理器包括控制硬件，其接收并存储控制值，并将控制值提供给微处理器的电路以控制微处理器的操作。微处理器还包括以预定值一起共同选择性地熔断的第一组多个熔丝，以及第二多个熔丝，其以从共同吹制到第一组熔丝中的预定值计算出的误差校正值一起共同选择性地吹制。响应于复位，微处理器读取第一和第二多个保险丝，使用从第二多个保险丝读取的值检测从第一多个保险丝读取的值中的错误，校正从第一多个保险丝读取的值使用从第二多个保险丝读取的值将保险丝恢复到预定值，并且使用校正的预定值将控制值写入控制硬件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式