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81. 发明授权

US07921300B2 Apparatus and method for secure hash algorithm 有权
标题翻译：用于安全散列算法的装置和方法
公开(公告)号：US07921300B2
公开(公告)日：2011-04-05
申请号：US10963427
申请日：2004-10-12
申请人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
IPC分类号： G06F12/14 , G06F9/30 , H04L9/32 , H04K1/00
CPC分类号： H04L9/3239 , G06F9/30007 , G06F9/30065 , G06F9/30185 , G06F9/3895 , G06F21/64 , G06F21/72 , H04L9/0643 , H04L2209/125 , H04L2209/60
摘要： An x86-compatible microprocessor that executes an application program fetched from memory, including a single, atomic hash instruction directing the x86-compatible microprocessor to perform the hash operation. The single, atomic hash instruction has an opcode field and a repeat prefix field. The opcode field prescribes that the x86-compatible microprocessor accomplish the hash operation. The repeat prefix field is coupled to the opcode field and indicates that the hash operation prescribed by the single, atomic hash instruction is to be accomplished on one or more message blocks. The x86-compatible microprocessor has a hash unit that is configured to execute a plurality of hash computations on each of the one or more message blocks to generate a corresponding intermediate hash value, where a last intermediate hash value that is computed for a last message block after processing all previous message blocks includes a message digest corresponding to the one or more message blocks.
摘要翻译：执行从存储器取出的应用程序的x86兼容微处理器，包括指示x86兼容微处理器执行散列操作的单个原子散列指令。单个原子散列指令具有操作码字段和重复前缀字段。操作码字段规定x86兼容微处理器完成散列操作。重复前缀字段耦合到操作码字段，并指示由单个原子散列指令规定的散列操作将在一个或多个消息块上完成。 x86兼容微处理器具有一个哈希单元，其被配置为在一个或多个消息块中的每一个上执行多个哈希计算，以生成对应的中间哈希值，其中为最后一个消息块计算的最后一个中间哈希值在处理之后，所有先前的消息块包括对应于一个或多个消息块的消息摘要。

82. 发明申请

US20110060892A1 SPECULATIVE FORWARDING OF NON-ARCHITECTED DATA FORMAT FLOATING POINT RESULTS 审中-公开
标题翻译：非结构化数据格式浮动点结果的统计转发
公开(公告)号：US20110060892A1
公开(公告)日：2011-03-10
申请号：US12820662
申请日：2010-06-22
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/302
CPC分类号： G06F7/483 , G06F2207/3824
摘要： A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands includes first and second floating-point units. The first floating-point unit is configured to speculatively forward a non-ADF result generated by the first floating-point unit to the second floating-point unit. The non-ADF result is associated with a first instruction. The second floating-point unit is configured to use the speculatively forwarded non-ADF result associated with the first instruction as a source operand to generate a result of a second instruction. The second floating-point unit is further configured to convert the non-ADF result to an ADF result and to determine whether the non-ADF result creates an exception condition when converted to the ADF result. The microprocessor is configured to cancel the second instruction, in response to determining that the non-ADF result creates an exception condition when converted to the ADF result.
摘要翻译：具有指定用于浮点操作数的至少一个架构数据格式（ADF）的指令集架构（ISA）的微处理器包括第一和第二浮点单元。第一浮点单元被配置为将由第一浮点单元生成的非ADF结果推测地转发到第二浮点单元。非ADF结果与第一条指令相关联。第二浮点单元被配置为使用与第一指令相关联的推测转发的非ADF结果作为源操作数来生成第二指令的结果。第二浮点单元还被配置为将非ADF结果转换为ADF结果，并且在转换为ADF结果时确定非ADF结果是否创建异常状态。响应于确定非ADF结果在转换为ADF结果时产生异常情况，微处理器被配置为取消第二指令。

83. 发明申请

US20110060785A1 FAST FLOATING POINT RESULT FORWARDING USING NON-ARCHITECTED DATA FORMAT 有权
标题翻译：使用非构建数据格式的快速浮点指示
公开(公告)号：US20110060785A1
公开(公告)日：2011-03-10
申请号：US12820578
申请日：2010-06-22
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/3824
摘要： A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The microprocessor includes a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result. The microprocessor also includes forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands.
摘要翻译：具有指定集架构（ISA）的微处理器，其指定用于浮点操作数的至少一个架构数据格式（ADF）。微处理器包括多个浮点单元，每个浮点单元包括被配置为接收非ADF源操作数并且对非ADF源操作数执行浮点运算以产生非ADF结果的算术单元。微处理器还包括转发总线，其配置为将多个浮点单元的每个运算单元产生的非ADF结果转发到多个浮点单元中的每一个，以供选择性使用，作为非ADF源操作数之一。

84. 发明申请

US20110055530A1 FAST REP STOS USING GRABLINE OPERATIONS 有权
标题翻译：快速回复使用格式操作
公开(公告)号：US20110055530A1
公开(公告)日：2011-03-03
申请号：US12781210
申请日：2010-05-17
申请人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker
发明人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker
IPC分类号： G06F9/38 , G06F12/08 , G06F9/312
CPC分类号： G06F9/30043 , G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3859 , G06F9/3865
摘要： A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line. The microprocessor foregoes initiating the transaction on the bus when executing the grabline instruction if the microprocessor determines that a store to the cache line would cause an exception.
摘要翻译：微处理器包括高速缓冲存储器和获取指令。该grabline指令指定一个内存地址，暗示内存的高速缓存行。获取指令指示微处理器在总线上启动零跳读取无效事务以获得高速缓存行的所有权。如果微处理器确定到高速缓存行的存储将导致异常，则微处理器在执行抓取指令时放弃在总线上启动事务。

85. 发明申请

US20100306475A1 DATA CACHE WITH MODIFIED BIT ARRAY 有权
标题翻译：数据缓存与修改的位阵列
公开(公告)号：US20100306475A1
公开(公告)日：2010-12-02
申请号：US12472845
申请日：2009-05-27
申请人： Rodney E. Hooker , Colin Eddy , G. Glenn Henry
发明人： Rodney E. Hooker , Colin Eddy , G. Glenn Henry
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831 , G06F9/30043 , G06F9/30047
摘要： A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array. The cache memory system reads both the first partial status and the second partial status to determine the full status.
摘要翻译：高速缓冲存储器系统包括：第一阵列的存储元件，每个存储元件被配置为存储高速缓存行;对应于第一存储元件阵列的存储元件的第二阵列，每个存储元件阵列被配置为将高速缓存行的第一部分状态存储在相应的存储元件中以及与所述第一阵列存储元件相对应的存储元件的第三阵列，每个存储元件被配置为将所述高速缓存线的第二部分状态存储在所述第一阵列的相应存储元件中。第二部分状态指示高速缓存行是否已被修改。当高速缓冲存储器系统修改第一阵列的存储元件内的高速缓存线时，它仅将第二部分状态写入第三阵列的相应存储元件中，以指示高速缓存线已被修改，但是避免写入第一部分状态在第二个阵列的相应的存储元素中。缓存存储器系统读取第一部分状态和第二部分状态以确定完整状态。

86. 发明授权

US07788433B2 Microprocessor apparatus providing for secure interrupts and exceptions 有权
标题翻译：提供安全中断和异常的微处理器设备
公开(公告)号：US07788433B2
公开(公告)日：2010-08-31
申请号：US12263154
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/00
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocessor accomplishes private bus transactions over the private bus to access the secure application program within the secure non-volatile memory. The private bus transactions are hidden from system bus resources and devices coupled to the system bus. The microprocessor includes normal interrupt logic and secure execution mode interrupt logic. The normal interrupt logic provides non-secure interrupts for interrupting the non-secure application programs when the microprocessor is operating in a non-secure mode. The secure execution mode interrupt logic provides secure interrupts when the microprocessor is operating in a secure mode, where the secure execution mode interrupt logic cannot be observed or accessed by the system bus resources or the non-secure application programs.
摘要翻译：一种用于执行安全代码的装置，具有经由专用总线经由系统总线与系统存储器耦合到安全非易失性存储器的微处理器。微处理器执行非安全应用程序和安全应用程序。微处理器通过专用总线实现专用总线交易，以访问安全非易失性存储器内的安全应用程序。专用总线事务隐藏在与系统总线相连的系统总线资源和设备上。微处理器包括正常的中断逻辑和安全的执行模式中断逻辑。当微处理器以非安全模式运行时，正常的中断逻辑提供用于中断非安全应用程序的非安全中断。当微处理器以安全模式工作时，安全执行模式中断逻辑提供安全中断，其中安全执行模式中断逻辑不能由系统总线资源或非安全应用程序访问。

87. 发明申请

US20100205399A1 PERFORMANCE COUNTER FOR MICROCODE INSTRUCTION EXECUTION 审中-公开
标题翻译： MICROCODE指令执行性能计数器
公开(公告)号：US20100205399A1
公开(公告)日：2010-08-12
申请号：US12370586
申请日：2009-02-12
申请人： Brent Bean , Jui-Shuan Chen , G. Glenn Henry , Terry Parks
发明人： Brent Bean , Jui-Shuan Chen , G. Glenn Henry , Terry Parks
IPC分类号： G06F9/32
CPC分类号： G06F11/3466 , G06F11/3471 , G06F2201/88
摘要： An apparatus for counting microcode instruction execution in a microprocessor includes a first register, a second register, a comparator, and a counter. The first register stores an address of a microcode instruction. The microcode instruction is stored in a microcode memory of the microprocessor. The second register stores an address of the next microcode instruction to be retired by a retire unit of the microprocessor. The comparator compares the addresses stored in the first and second registers to indicate a match between them. The counter counts the number of times the comparator indicates a match between the addresses stored in the first register and the second register. The first register is user-programmable and the counter is user-readable. A mask register may be included to create a range of microcode memory addresses so that executions of microcode instructions within the range are counted.
摘要翻译：用于计数微处理器中微代码指令执行的装置包括第一寄存器，第二寄存器，比较器和计数器。第一个寄存器存储微码指令的地址。微代码指令存储在微处理器的微代码存储器中。第二寄存器存储由微处理器的退出单元退出的下一微代码指令的地址。比较器比较存储在第一和第二寄存器中的地址，以指示它们之间的匹配。计数器计数比较器指示存储在第一个寄存器和第二个寄存器中的地址之间的匹配次数。第一个寄存器是用户可编程的，计数器是用户可读的。可以包括掩码寄存器来创建微码存储器地址的范围，从而对范围内的微代码指令的执行进行计数。

88. 发明授权

US07712105B2 Microprocessor including random number generator supporting operating system-independent multitasking operation 有权
标题翻译：微处理器包括随机数发生器，支持独立于操作系统的多任务操作
公开(公告)号：US07712105B2
公开(公告)日：2010-05-04
申请号：US11428308
申请日：2006-06-30
申请人： G. Glenn Henry , Terry Parks , Arturo Martin-de-Nicolas
发明人： G. Glenn Henry , Terry Parks , Arturo Martin-de-Nicolas
IPC分类号： G06F9/46 , G06F1/02 , G06F9/44
CPC分类号： G06F9/30101 , G06F9/3863 , G06F9/461
摘要： A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of random numbers. The CSR is not saved and restored by the OS. The RNG shadows the CSR with an SSE register that is saved and restored by the OS. A new instruction loads the CSR, and also loads the shadowed SSE register. Whenever the SSE register is restored from memory, the RNG sets a flag indicating that a possible task switch occurred. Whenever the processor executes a new instruction that stores the random data to memory, it checks the flag and copies the control values from the SSE register to the CSR if the flag is true, discards previously generated bytes, and restarts random number generation.
摘要翻译：一个微处理器，包括一个随机数发生器（RNG），可以在没有操作系统（OS）支持的情况下在任务交换机上保存和恢复其自身状态。 RNG包括用于存储影响随机数生成的控制值的控制和状态寄存器（CSR）。 CSR不会由操作系统保存和恢复。 RNG使用由操作系统保存和恢复的SSE寄存器来影响CSR。一个新的指令加载了CSR，并加载了阴影的SSE寄存器。每当从内存中恢复SSE寄存器时，RNG设置一个标志，指示可能的任务切换发生。每当处理器执行将随机数据存储到存储器的新指令时，它检查标志，并将控制值从SSE寄存器复制到CSR，如果标志为真，则丢弃先前生成的字节，并重新启动随机数生成。

89. 发明申请

US20100070741A1 MICROPROCESSOR WITH FUSED STORE ADDRESS/STORE DATA MICROINSTRUCTION 有权
标题翻译：具有熔接存储地址/存储数据微处理器的微处理器
公开(公告)号：US20100070741A1
公开(公告)日：2010-03-18
申请号：US12233261
申请日：2008-09-18
申请人： Gerard M. Col , G. Glenn Henry , Rodney E. Hooker , Terry Parks
发明人： Gerard M. Col , G. Glenn Henry , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/22
CPC分类号： G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/3836 , G06F9/3857
摘要： A microprocessor includes an instruction translator that translates a store macroinstruction into exactly one fused store microinstruction. The store macroinstruction in the microprocessor's macroarchitecture macroinstruction set instructs the microprocessor to store data from a general purpose register of the microprocessor to a memory location. The fused store microinstruction is an instruction in the microprocessor's microarchitecture microinstruction set. A reorder buffer (ROB) receives the fused store microinstruction from the instruction translator into exactly one of its plurality of entries. An instruction dispatcher dispatches for execution a store address microinstruction and a store data microinstruction to different respective execution units of the microprocessor in response to receiving the fused store microinstruction. Neither the store address microinstruction nor the store data microinstruction occupy any of the ROB entries. The ROB retires the fused store microinstruction after being notified that both the store address microinstruction and the store data microinstruction have been executed.
摘要翻译：一个微处理器包括一个指令翻译器，将一个存储宏指令转换成一个融合存储微指令。微处理器微架构宏指令集中的存储宏指令指示微处理器将数据从微处理器的通用寄存器存储到存储器位置。融合存储微指令是微处理器微架构微指令集中的指令。重排序缓冲器（ROB）将熔接存储微指令从指令转换器接收到其多个条目中的正好一个。响应于接收到融合存储微指令，指令调度器调度用于执行存储地址微指令和存储数据微指令到微处理器的不同相应执行单元。商店地址微指令也不存储数据微指令占用任何ROB条目。在通知存储地址微指令和存储数据微指令已被执行之后，ROB将退出融合存储微指令。

90. 发明授权

US07664810B2 Microprocessor apparatus and method for modular exponentiation 有权
标题翻译：用于模幂的微处理器装置和方法
公开(公告)号：US07664810B2
公开(公告)日：2010-02-16
申请号：US11130472
申请日：2005-05-16
申请人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
IPC分类号： G06F7/38 , H04L9/00
CPC分类号： G06F7/728 , G06F9/3001 , G06F9/3017 , G06F9/30174
摘要： A technique is provided for performing modular multiplication. In one embodiment, an apparatus in a microprocessor is provided for accomplishing modular multiplication operations. The apparatus includes translation logic and execution logic. The translation logic receives an atomic Montgomery multiplication instruction from a source therefrom, where the atomic Montgomery multiplication instruction prescribes generation of a Montgomery product. The translation logic translates the atomic Montgomery multiplication instruction into a sequence of micro instructions specifying sub-operations required to accomplish generation of the Montgomery product. The execution logic is operatively coupled to the translation logic. The execution logic receives the sequence of micro instructions, and performs the sub-operations to generate the Montgomery product.
摘要翻译：提供了一种用于执行模乘法的技术。在一个实施例中，微处理器中的装置被提供用于完成模数乘法运算。该装置包括翻译逻辑和执行逻辑。翻译逻辑从其源头接收原始的蒙哥马利乘法指令，其中原子蒙哥马利乘法指令规定了蒙哥马利产品的生成。翻译逻辑将原始蒙哥马利乘法指令转换为指定完成蒙哥马利产品生成所需的子操作的微指令序列。执行逻辑可操作地耦合到翻译逻辑。执行逻辑接收微指令序列，并执行子操作以产生蒙哥马利产品。

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