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81. 发明授权

US07961504B2 Phase change random access memory device and related methods of operation 有权
标题翻译：相变随机存取存储器件及相关操作方法
公开(公告)号：US07961504B2
公开(公告)日：2011-06-14
申请号：US12724679
申请日：2010-03-16
申请人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim
发明人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0092
摘要： A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.
摘要翻译：操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

82. 发明授权

US07949928B2 Semiconductor memory device and data error detection and correction method of the same 失效
标题翻译：半导体存储器件和数据错误检测与校正方法相同
公开(公告)号：US07949928B2
公开(公告)日：2011-05-24
申请号：US11773214
申请日：2007-07-03
申请人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
发明人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1076 , G11C8/04 , G11C8/12
摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
摘要翻译：半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为检测并输出校正的读取数据。

83. 发明授权

US07944741B2 Apparatus and systems using phase change memories 有权
标题翻译：使用相变存储器的装置和系统
公开(公告)号：US07944741B2
公开(公告)日：2011-05-17
申请号：US12611606
申请日：2009-11-03
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要翻译：提供了使用相变存储器件的装置和系统。相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多个复位线中相应的一个。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

84. 发明申请

US20100329057A1 Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation 有权
标题翻译：对执行读写操作的非易失性半导体存储器件的位线进行放电的方法
公开(公告)号：US20100329057A1
公开(公告)日：2010-12-30
申请号：US12662512
申请日：2010-04-21
申请人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
发明人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2213/72 , G11C2213/79
摘要： In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. the method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.
摘要翻译：在执行读写操作的非易失性半导体存储器件的放电位线的方法中。该方法包括在第一周期内基于写入命令将全局写入位线放电到接地电压。该方法还包括在第二周期期间将全局写入位线的放电电压维持在接地电压中。

85. 发明授权

US07859882B2 Resistive memory device and method of writing data 有权
标题翻译：电阻式存储器件及数据写入方法
公开(公告)号：US07859882B2
公开(公告)日：2010-12-28
申请号：US11844511
申请日：2007-08-24
申请人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang
发明人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C13/00 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2213/79
摘要： A resistive memory device is provided. The resistive memory device includes word lines arranged in M rows, bit lines arranged in N columns, local source lines arranged in M/2 rows, and resistive memory cells arranged in M rows and N columns. Each of the resistive memory cells includes a resistance variable element having a first electrode connected to a corresponding bit line, and a cell transistor having a first terminal connected to a second electrode of the resistance variable element, a second terminal connected to a corresponding local source line, and a control terminal connected to a corresponding word line. The local source line is commonly connected to the second terminals of the cell transistors of the two neighboring rows.
摘要翻译：提供了一种电阻式存储器件。电阻式存储装置包括排列成M行的字线，以N列排列的位线，以M / 2行排列的局部源极线以及布置成M行N列的电阻存储单元。每个电阻存储单元包括电阻可变元件，电阻可变元件具有连接到对应的位线的第一电极，以及单元晶体管，其具有连接到电阻可变元件的第二电极的第一端子，连接到相应的本地源极的第二端子线路和连接到相应字线的控制终端。本地源极线通常连接到两个相邻行的单元晶体管的第二端子。

86. 发明授权

US07746688B2 PRAM and method of firing memory cells 有权
标题翻译： PRAM和烧存存储单元的方法
公开(公告)号：US07746688B2
公开(公告)日：2010-06-29
申请号：US11933536
申请日：2007-11-01
申请人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim , Woo-yeong Cho , Chang-han Choi , Ki-won Lim
发明人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim , Woo-yeong Cho , Chang-han Choi , Ki-won Lim
IPC分类号： G11C11/00
CPC分类号： G11C8/06 , G11C8/10 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/12005 , G11C29/50 , G11C2013/0083 , G11C2013/0092
摘要： A PRAM includes a memory cell array of phase change memory cells, and a write circuit receiving an externally provided first voltage and supplying a write pulse for writing data to the memory cells in a normal operation mode. The write circuit also receives an externally provided second voltage higher than the first voltage and supplies a firing pulse to at least one firing-failed phase change memory cell.
摘要翻译： PRAM包括相变存储单元的存储单元阵列和接收外部提供的第一电压的写入电路，并且在正常操作模式中提供用于将数据写入存储单元的写入脉冲。写入电路还接收高于第一电压的外部提供的第二电压，并且向至少一个点火故障相变存储单元提供点火脉冲。

87. 发明授权

US07729160B2 Phase-change random access memory 有权
标题翻译：相变随机存取存储器
公开(公告)号：US07729160B2
公开(公告)日：2010-06-01
申请号：US11616969
申请日：2006-12-28
申请人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C29/808 , G11C29/02 , G11C29/027 , G11C29/787 , G11C29/804 , G11C29/846
摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.
摘要翻译：相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量控制信号。

88. 发明申请

US20100085799A1 METHOD OF DRIVING MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE AND MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE 有权
标题翻译：驱动多级可变电阻记忆装置和多级可变电阻记忆装置的方法
公开(公告)号：US20100085799A1
公开(公告)日：2010-04-08
申请号：US12632018
申请日：2009-12-07
申请人： Woo-Yeong CHO , Ki-Sung KIM , Du-Eung KIM , Kwang-Jin LEE , Jun-Soo BAE
发明人： Woo-Yeong CHO , Ki-Sung KIM , Du-Eung KIM , Kwang-Jin LEE , Jun-Soo BAE
IPC分类号： G11C11/00 , G11C7/02 , G11C7/00
CPC分类号： G11C11/5678 , G11C7/04 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0078 , G11C2211/5634
摘要： Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.
摘要翻译：公开了一种驱动多电平可变电阻存储器件的方法。驱动多电平可变电阻存储器件的方法包括向可变电阻存储器单元提供写入电流，以便改变可变电阻存储器单元的电阻，验证改变的电阻是否进入预定的电阻窗，预期电阻窗口，取决于参考单元的电阻，并且基于验证结果从最近提供的写入电流提供具有增加或减少的量的写入电流，以便改变可变电阻存储单元的电阻。

89. 发明申请

US20100080039A1 Nonvoltile memory device and method of driving the same 有权
标题翻译：非挥发性记忆装置及其驱动方法
公开(公告)号：US20100080039A1
公开(公告)日：2010-04-01
申请号：US12585728
申请日：2009-09-23
申请人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Hye-Jin Kim
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00 , G11C7/02
CPC分类号： G11C13/0023 , G11C7/02 , G11C7/12 , G11C7/18 , G11C13/00 , G11C13/0004 , G11C13/0026
摘要： A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors.
摘要翻译：提供一种非易失性存储器件及其驱动方法，其采用改进的写入操作。驱动非易失性存储器件的方法包括提供包括多个存储体的非易失性存储器件，每个存储器组具有多个局部位线和多个可变电阻存储器单元; 选择性地连接读取全局位线用于与局部位线一起读取数据，并且首先通过连接耦合到读出的全局位线的局部位线放电晶体管来放电选择性连接的局部位线; 并选择性地连接用于将数据写入本地位线的写入全局位线，以及其次通过导通全局位线放电晶体管对选择连接的局部位线进行放电。

90. 发明授权

US07688620B2 Nonvolatile memory device and related methods of operation 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US07688620B2
公开(公告)日：2010-03-30
申请号：US11834843
申请日：2007-08-07
申请人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
发明人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064
摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.
摘要翻译：在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

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