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81. 发明申请

US20090219764A1 Semiconductor memory device for high-speed data input / output 有权
标题翻译：用于高速数据输入/输出的半导体存储器件
公开(公告)号：US20090219764A1
公开(公告)日：2009-09-03
申请号：US12217019
申请日：2008-06-30
申请人： Beom-Ju Shin , Sang-Sic Yoon
发明人： Beom-Ju Shin , Sang-Sic Yoon
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1018 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1078 , G11C2207/107
摘要： Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data.
摘要翻译：用于高速数据输入/输出的半导体存储器件包括：第一串行器，被配置为部分地串行输入8位并行数据以输出第一至第四串行数据;第二串行器，被配置为部分串行化第一至第四串行数据以输出第五和第五串行数据; 第六串行数据和第三串行器，被配置为串行化第五和第六串行数据以输出第七串行数据。

82. 发明授权

US07538698B2 Apparatus and method of generating DBI signal in semiconductor integrated circuit 有权
标题翻译：在半导体集成电路中产生DBI信号的装置和方法
公开(公告)号：US07538698B2
公开(公告)日：2009-05-26
申请号：US11826765
申请日：2007-07-18
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： H03M5/00
CPC分类号： G11C7/1006 , G11C7/1048 , G11C7/1051 , G11C7/1063
摘要： An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry terminal, each of which receives data, performs an operation on the received data, and outputs a sum and a carry. A DBI determining unit determines a logic value of each of the data on the basis of the sum and the carry that are transmitted from the full adder, and generates a DBI signal.
摘要翻译：一种用于在半导体集成电路中产生DBI信号的装置包括一个全加器，它包括数据输入端和一个进位端，每个进位端接收数据，对接收到的数据执行一个操作，并输出一个和和一个进位。 DBI确定单元基于从全加器发送的和和进位来确定每个数据的逻辑值，并生成DBI信号。

83. 发明申请

US20080232180A1 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080232180A1
公开(公告)日：2008-09-25
申请号：US11819564
申请日：2007-06-28
申请人： Jee-Yul Kim , Beom-Ju Shin
发明人： Jee-Yul Kim , Beom-Ju Shin
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066
摘要： A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock signal; an internal command signal generator for generating an internal command signal in response to an external command; a delay circuit for delaying the internal command signal by a delay time corresponding to a delay time of the DLL to output a delayed internal command signal; and an output enable signal generator for generating an output enable signal based on the delayed internal command signal and the DLL clock signal.
摘要翻译：半导体存储器件包括：延迟锁定环（DLL），用于延迟外部时钟以产生DLL时钟信号; 内部命令信号发生器，用于响应于外部命令产生内部命令信号; 延迟电路，用于将所述内部命令信号延迟与所述DLL的延迟时间对应的延迟时间，以输出延迟的内部命令信号; 以及输出使能信号发生器，用于基于延迟的内部命令信号和DLL时钟信号产生输出使能信号。

84. 发明授权

US07355899B2 Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure 有权
标题翻译：具有改进结构的多位预取型半导体存储器件的管锁存电路
公开(公告)号：US07355899B2
公开(公告)日：2008-04-08
申请号：US11158345
申请日：2005-06-22
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/103 , G11C7/1039 , G11C7/106
摘要： Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit includes: a first latch circuit for simultaneously latching K-bit input data (K is an integer), which is received by simultaneously pre-fetching from an internal core circuit through global input/output lines, in response to an input latch control signal; a first multiplexing circuit for selecting K/2-bit input data among K-bit input data in response to a first selection control signal; a second multiplexing circuit for selecting 2-bit input data among the K/2-bit input data in response to a second selection control signal; and a second latch circuit for alternately latching the 2-bit data to sequentially output the latch data as output data in response to output latch control signals. The invention cuts down the overall chip size and current consumption of the pipe latch circuit by reducing the number of multiplexers necessary for arranging the pre-fetched data in a predetermined output order.
摘要翻译：提供具有先进结构的多位预取型半导体存储器件的管锁存电路。管锁存电路包括：第一锁存电路，用于同时锁存通过全局输入/输出线从内部核心电路同时预取的K位输入数据（K为整数），其响应于输入锁存控制信号; 用于响应于第一选择控制信号在K位输入数据中选择K / 2位输入数据的第一复用电路; 第二复用电路，用于响应于第二选择控制信号在K / 2位输入数据中选择2位输入数据; 以及第二锁存电路，用于响应于输出锁存控制信号交替地锁存2位数据以顺序输出锁存数据作为输出数据。本发明通过减少以预定输出顺序排列预取数据所需的多路复用器的数量来减少管锁存电路的整体芯片尺寸和电流消耗。

85. 发明授权

US07345930B2 Write circuit of memory device 有权
标题翻译：存储器件的写电路
公开(公告)号：US07345930B2
公开(公告)日：2008-03-18
申请号：US11476562
申请日：2006-06-29
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C7/06
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1096 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value.
摘要翻译：半导体存储器件的写入电路包括全局数据输入/输出（I / O）线; 放大块，用于接收和放大写入数据，并将放大的写入数据作为全局数据发送到全局数据I / O线上; 以及控制块，用于将写入数据与全局数据进行比较，从而当写入数据和全局数据具有基本相同的数据值时禁止放大块。

86. 发明授权

US07209393B2 Semiconductor memory device and method for multiplexing write data thereof 有权
标题翻译：半导体存储器件及其写入数据的多路复用方法
公开(公告)号：US07209393B2
公开(公告)日：2007-04-24
申请号：US11153338
申请日：2005-06-16
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： G11C7/10
CPC分类号： G11C11/4097 , G11C7/10 , G11C7/1078 , G11C7/1096 , G11C2207/002
摘要： A semiconductor memory device including a write multiplexer unit that multiplexes write data transmitted to a global I/O bus disposed in front of a write driver. The semiconductor memory device further includes a memory core region including an array of memory cells, a data input path that receives data to be written into the memory cells from the outside, a first bus that receives the data through the data input path, a multiplexing unit that multiplexes the data received from the first bus, and a driving unit that selects and drives the multiplexed data.
摘要翻译：一种半导体存储器件，包括多路复用发送到写入驱动器前面的全局I / O总线的写入数据的写入多路复用器单元。半导体存储器件还包括存储器核心区域，其包括存储器单元阵列，从外部接收要写入存储器单元的数据的数据输入路径，通过数据输入路径接收数据的第一总线，多路复用多路复用从第一总线接收的数据的单元，以及选择并驱动多路复用数据的驱动单元。

87. 发明申请

US20070070774A1 Memory device having latch for charging or discharging data input/output line 有权
标题翻译：具有用于对数据输入/输出线进行充电或放电的锁存器的存储器件
公开(公告)号：US20070070774A1
公开(公告)日：2007-03-29
申请号：US11477529
申请日：2006-06-30
申请人： Sang-Jin Byeon , Beom-Ju Shin
发明人： Sang-Jin Byeon , Beom-Ju Shin
IPC分类号： G11C8/00
CPC分类号： G11C7/1048
摘要： A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.
摘要翻译：具有用于执行读或写操作的活动状态和除活动状态之外的非活动状态的所要求保护的发明的半导体存储器件包括数据输入/输出（I / O）线; 上拉锁存单元，用于在半导体存储器件处于非活动状态时拉起数据I / O线; 一个下拉锁存单元，用于在半导体存储器件处于非活动状态时下拉数据I / O线; 以及选择单元，用于选择性地驱动上拉锁存单元和下拉锁存单元中的一个。

88. 发明申请

US20060092722A1 Data arrangement control signal generator for use in semiconductor memory device 失效
标题翻译：用于半导体存储器件的数据排列控制信号发生器
公开(公告)号：US20060092722A1
公开(公告)日：2006-05-04
申请号：US11024458
申请日：2004-12-30
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C7/1018 , G11C7/1039
摘要： A data arrangement control signal generation circuit for use in a semiconductor memory device includes a plurality of data arrangement control signal generation units connected in series, each for selectively generating a data arrangement control signal according to a column address strobe (CAS) latency.
摘要翻译：用于半导体存储器件的数据排列控制信号产生电路包括串联连接的多个数据排列控制信号生成单元，每个用于根据列地址选通（CAS）等待时间选择性地产生数据排列控制信号。

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