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71. 发明授权

US5414415A Cross-connect apparatus capable of avoiding a superfluous detour route therein 失效
标题翻译：能够避免其中多余的绕行路线的交叉连接装置
公开(公告)号：US5414415A
公开(公告)日：1995-05-09
申请号：US15651
申请日：1993-02-09
申请人： Hiromi Ueda , Ikuo Tokizawa , Kazuo Iguchi , Haruo Yamashita , Takatoshi Kurano , Motoo Nishihara
发明人： Hiromi Ueda , Ikuo Tokizawa , Kazuo Iguchi , Haruo Yamashita , Takatoshi Kurano , Motoo Nishihara
IPC分类号： H04Q3/52 , H04L12/931 , H04L12/933 , H04Q11/04 , H01H67/00
CPC分类号： H04L49/104 , H04L49/15 , H04L2012/561
摘要： In a cross-connect apparatus for use in selectively connecting a plurality of input transmission paths to a plurality of output transmission paths, each of the input and the output transmission paths is divided into first through m-th groups each of which is composed of first through n-th transmission paths, first through m-th elementary switch modules are located between the input and the output transmission paths, n in number, of the first through the m-th groups and are connected to a connection switch module through first to m-th input internal path groups each of which is composed of n internal paths and which are extended into first through m-th switch units each of which has input terminals, n(m-1) in number, and output terminals, n in number, where n and m are natural numbers. An i-th one of the switch units in the connection switch module is connected to the input path groups, (m-1) in number, except an i-th internal path group, where i is a natural number between unity and m, both inclusive. The output terminals of the i-th switch unit is connected to an i-th one of the elementary switch modules through an i-th one of output internal paths. This structure serves to avoid an unnecessary detour route in the cross-connect apparatus.
摘要翻译：在用于选择性地将多个输入传输路径连接到多个输出传输路径的交叉连接装置中，输入和输出传输路径中的每一个被分成第一至第m组，每个组由第一组通过第n个传输路径，第一到第m个基本交换模块位于第一至第m组的输入和输出传输路径之间，n个数量上，并且首先通过连接交换模块连接到第m个输入内部路径组，每个由n个内部路径组成，并且被扩展到第一至第m个开关单元，每个开关单元具有输入端子，数量为n（m-1），输出端子n 数，其中n和m是自然数。连接开关模块中的第i个开关单元连接到输入路径组（m-1），除了第i个内部路径组，其中i是单位和m之间的自然数，包括在内第i个开关单元的输出端通过第i个输出内部通路连接到基本开关模块的第i个。该结构用于避免交叉连接装置中的不必要的迂回路径。

72. 发明授权

US5410540A Shared-buffer-type ATM switch having copy function and copy method thereof 失效
标题翻译：具有复制功能的共享缓冲型ATM交换机及其复制方法
公开(公告)号：US5410540A
公开(公告)日：1995-04-25
申请号：US132999
申请日：1993-10-07
申请人： Kiyoshi Aiki , Takahiko Kozaki , Noboru Endo , Haruo Shibata
发明人： Kiyoshi Aiki , Takahiko Kozaki , Noboru Endo , Haruo Shibata
IPC分类号： H04Q3/52 , H04L12/18 , H04L12/931 , H04Q11/04
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/309 , H04L2012/5672
摘要： In a shared-buffer-type ATM switch including a multiplexer, a shared buffer memory, a demultiplexer, a buffer memory controller, a cell copy section is disposed between the multiplexer and the memory. The copy section produces a plurality of copies of a broadcast cell according to information of a copy information table and adds associate routing information to each copied cell so as to write the cells in the memory. In response to an indication from an output counter, the cells are read from the memory to be distributed to output ports, thereby implementing a broadcast function.
摘要翻译：在包括多路复用器，共享缓冲存储器，解复用器，缓冲存储器控制器的共享缓冲器型ATM交换机中，单元复制部分设置在多路复用器和存储器之间。复制部分根据复制信息表的信息产生广播小区的多个副本，并将关联路由信息添加到每个复制的小区，以便将单元写入存储器。响应于来自输出计数器的指示，从存储器读取单元以分配到输出端口，从而实现广播功能。

73. 发明授权

US5383183A Data communication equipment 失效
标题翻译：数据通信设备
公开(公告)号：US5383183A
公开(公告)日：1995-01-17
申请号：US935833
申请日：1992-08-26
申请人： Atsushi Yoshida
发明人： Atsushi Yoshida
IPC分类号： H04Q3/52 , H04Q11/04
CPC分类号： H04Q11/04
摘要： Data communication equipment incorporating a matrix switch 11 and a control section 19 in which the matrix switch 11 is provided between M terminal interface units 12.sub.1 -12.sub.M and N communication channel interface units 13.sub.1 -13.sub.N and is capable of switching the combination of the N communication channels 10.sub.1 -10.sub.N and the M data terminal units 18.sub.1 -18.sub.M to enable mutual connections between a desired pair of communication channel and interface units. The controller 19 controls the matrix switch 11 and prescribes the appropriate connections between one of the N communication channel interface units 13.sub.1 -13.sub.N and one of the M terminal interface units 12.sub.1 -12.sub.M. Both the N communication channel interface units 13.sub.1 -13.sub.N and the M terminal interface units 12.sub.1 -12.sub.M are capable of inserting or extracting the connections to the matrix switch 11 on a unit-to-unit basis by means of a pair of N terminal groups 15.sub.1 -15.sub.N and M terminal interface units 14.sub.1 -14.sub.M, both of which are designed to allow insertion and extraction. Among the terminal interface units to be included herein are the LAN interface units originally designed to be used with a LAN system, a router, a bus and a protocol converter.
摘要翻译：包含矩阵开关11和控制部分19的数据通信设备，其中矩阵开关11设置在M个终端接口单元121-12M和N个通信信道接口单元131 -13N之间，并且能够切换N个通信信道 101-10N和M个数据终端单元181-18M，以实现期望的一对通信信道和接口单元之间的相互连接。控制器19控制矩阵开关11，并且规定了N个通信信道接口单元131-13N之一和M个终端接口单元121-12M中的一个之间的适当连接。 N个通信信道接口单元131-13N和M个终端接口单元121-12M能够通过一对N个终端组151在单元到单元的基础上插入或提取到矩阵开关11的连接 -15N和M端子接口单元141-14M，它们都被设计成允许插拔。这里要包括的终端接口单元是最初设计为与LAN系统，路由器，总线和协议转换器一起使用的LAN接口单元。

74. 发明授权

US5373393A Opical interferometric device with spatial light modulators for switching substantially coherent light 失效
标题翻译：具有用于切换基本相干光的空间光调制器的光学干涉仪
公开(公告)号：US5373393A
公开(公告)日：1994-12-13
申请号：US69501
申请日：1993-06-01
申请人： Michael C. DeJule , Nabeel A. Riza , Donald E. Castleberry , Thomas L. Credelle
发明人： Michael C. DeJule , Nabeel A. Riza , Donald E. Castleberry , Thomas L. Credelle
IPC分类号： G02B27/14 , G02B27/28 , G02F1/315 , H04Q3/52 , G02B1/00
CPC分类号： G02B27/144 , G02B27/145 , G02B27/28 , G02F1/315
摘要： An interferometric optical switching device for switching substantially coherent light beams includes a plurality of interferometric switching cells arranged in matrix form. Each interferometric switching cell is independently controllable to selectively direct received light beams along at least a selected one of two axes. The device can be three-dimensionally expanded to increase the number of ports to which the light beams can be selectively switched, in which case the matrices can share integrally constructed interferometric switching cells. The device is further capable of providing bidirectional communication between predetermined ones of the ports thereof.
摘要翻译：用于切换基本相干光束的干涉光学开关装置包括以矩阵形式布置的多个干涉式开关单元。每个干涉式开关单元是可独立控制的，以便沿两个轴中的至少一个选择性地引导接收的光束。该装置可以被三维地扩展以增加可以选择性地切换光束的端口的数量，在这种情况下，矩阵可以共享整体构造的干涉式开关单元。该设备还能够在其预定端口之间提供双向通信。

75. 发明授权

US5371495A Deterministic routing method for minimal switch circuits 失效
标题翻译：最小开关电路的确定性路由方法
公开(公告)号：US5371495A
公开(公告)日：1994-12-06
申请号：US824940
申请日：1992-01-24
申请人： Jay J. Sturges , Richard P. Vireday
发明人： Jay J. Sturges , Richard P. Vireday
IPC分类号： H04Q3/52 , H04Q3/68 , H04Q3/00
CPC分类号： H04Q3/685 , H04Q3/523 , Y10T307/74 , Y10T307/747 , Y10T307/76
摘要： A deterministic routing method for switch matrices. The routed matrix receives N input signals and produces M output signals on M output columns. The method of the present invention has three steps. First, each of the M output columns in the switch matrix is searched for each of N separate input signals. Secondly, each of the N inputs is assigned to its located column. If all of the N inputs cannot be assigned to one of the M columns, the set of inputs is shifted and the steps are repeated until all of the N inputs are routed.
摘要翻译：一种用于开关矩阵的确定性路由方法。路由矩阵接收N个输入信号，并在M个输出列上产生M个输出信号。本发明的方法有三个步骤。首先，搜索开关矩阵中的每个M个输出列，分别输入N个独立的输入信号。其次，将N个输入中的每一个分配给其定位的列。如果所有N个输入都不能分配给M列中的一个，则输入集合被移位，并重复这些步骤，直到所有N个输入都被路由为止。

76. 发明授权

US5365358A Optical switching equipment for the through-connection of optical message cells 失效
标题翻译：光交换设备用于通过光信息单元的连接
公开(公告)号：US5365358A
公开(公告)日：1994-11-15
申请号：US110995
申请日：1993-08-24
申请人： Karl-Ulrich Stein
发明人： Karl-Ulrich Stein
IPC分类号： H04B10/02 , H04L12/56 , H04Q3/00 , H04Q3/52 , H04Q11/00 , H04Q11/04 , H04J14/00
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1576 , H04Q11/0001 , H04L2012/5605 , H04Q11/0066
摘要： An optical switching network for through-connecting optical message cells has at least one optical space-switching multiple connected at its input side to the inputs thereof and has at least one optical transit time harp formed with a plurality of light waveguides with graduated transit times of whole-number, n-multiples (with n.gtoreq.0) of the message cell duration. The outputs of a transit time harp following a space-switching multiple are respectively combined to a concentrator output of the optical switching network.
摘要翻译：用于通过连接光信息单元的光交换网络具有至少一个在其输入侧连接到其输入端的光学空间交换多路复用器，并具有形成有多个光波导的至少一个光学渡越时间竖条，消息单元持续时间的整数，n倍数（n> / = 0）。空中交换多路复用后的通行时间竖琴的输出分别组合到光交换网络的集中器输出。

77. 发明授权

US5355372A Threshold-based load balancing in ATM switches with parallel switch planes related applications 失效
标题翻译：具有并行交换平面相关应用的ATM交换机中基于阈值的负载平衡
公开(公告)号：US5355372A
公开(公告)日：1994-10-11
申请号：US107542
申请日：1993-08-17
申请人： Bhaskar Sengupta , Shyamal Chowdhury
发明人： Bhaskar Sengupta , Shyamal Chowdhury
IPC分类号： H04B10/02 , H04L12/56 , H04Q3/52 , H04L12/50 , H04L12/54
CPC分类号： H04L49/3081 , H04L49/1523 , H04L49/1553 , H04L49/50 , H04L2012/568 , H04L49/30
摘要： An asynchronous transfer mode switching system uses a parallel array of switching planes, distributors for distributing cells between the switching planes, and resequencers for collecting the cells after they have been switched. To balance the loads in the output buffers of the switching planes, each distributor includes two one-cell buffers and a load matrix. The load matrix stores the state of the output buffers in the switching planes, and this information is used to decide whether to send a cell arriving at the first of the one-cell buffers to its scheduled switching plane or to store the cell in the other of the one-cell buffers until either a switching plane with a lightly loaded output buffer for the cell's destination becomes available or another later arriving cell needs to be stored there.
摘要翻译：异步传输模式切换系统使用并行阵列的交换平面，用于在交换平面之间分配小区的分配器，以及用于在切换之后收集小区的调度器。为了平衡开关平面的输出缓冲器中的负载，每个分配器包括两个单电池缓冲器和负载矩阵。负载矩阵将输出缓冲器的状态存储在切换平面中，并且该信息用于决定是否将到达第一单电池缓冲器的单元发送到其调度的交换平面，或将该单元存储在另一个直到具有用于小区目的地的轻载输出缓冲器的切换平面变得可用，或者另一个后来到达的小区需要存储在那里。

78. 发明授权

US5345228A Very large scale modular switch 失效
标题翻译：非常大规模的模块化开关
公开(公告)号：US5345228A
公开(公告)日：1994-09-06
申请号：US785730
申请日：1991-10-31
申请人： Peter A. Franaszek , Christos J. Georgiou
发明人： Peter A. Franaszek , Christos J. Georgiou
IPC分类号： H04Q3/52 , G06F15/173 , H04Q11/04 , H04Q1/00
CPC分类号： H04Q11/0407
摘要： Switch resources for a one-sided crosspoint switch with distributed control (i.e., switch ports, internal busses and controllers) have been organized so that modular growth is facilitated by: (1) assigning each switch port uniquely to one of the controllers; (2) making each controller handle only the crosspoints connected to the switch ports assigned to it; (3) assigning each internal bus uniquely to one of the controllers; and (4) providing a network for the controllers to communicate with each other.
摘要翻译：已经组织了具有分布式控制（即，交换机端口，内部总线和控制器）的单向交叉点交换机的资源切换，以便通过以下方式促进模块化增长：（1）将每个交换机端口唯一地分配给控制器之一; （2）使每个控制器仅处理连接到分配给它的交换机端口的交叉点; （3）将每条内部总线唯一地分配给其中一个控制器; 和（4）提供用于控制器相互通信的网络。

79. 发明授权

US5339311A Data packet resequencer for a high speed data switch 失效
标题翻译：高速数据交换机的数据包重新平衡器
公开(公告)号：US5339311A
公开(公告)日：1994-08-16
申请号：US5587
申请日：1993-01-19
申请人： Jonathan S. Turner
发明人： Jonathan S. Turner
IPC分类号： H04Q3/00 , H04L12/56 , H04Q3/52 , H04Q11/04
CPC分类号： H04L49/3081 , H04L49/30 , H04L49/501 , H04Q11/0478 , H04L2012/5646 , H04L2012/565
摘要： A resequencing buffer and buffer control circuit is disclosed for resequencing data packets into their timed sequence after traversing a switch fabric which can introduce a misordering of data packets because of the varying time intervals required for data packets to traverse the switch fabric in a non-blocking manner. The resequencing buffer controller includes a plurality of hi-directional shift registers for storing each data packet's age and slot number, each bi-directional shift register having an associated slot control circuit for feeding the age and slot number one bit at a time onto a contention bus to thereby determine the oldest data packet eligible for transmission. The contention bus is an exclusive OR wire bus which interconnects the slot control circuits and an output circuit which controls the buffer to output the slot number containing the data packet of oldest age. In the event of ties between data packets having the same age, the slot numbers of the buffer are used to select a data packet for transmission.
摘要翻译：公开了一种重新排序缓冲器和缓冲器控制电路，用于在遍历交换结构之后将数据分组重新排序成其定时序列，由于数据分组在非阻塞中遍历交换结构所需的变化的时间间隔，其可能引入数据分组的错误方式。重新排序缓冲器控制器包括多个用于存储每个数据分组的年龄和时隙号的高位移位寄存器，每个双向移位寄存器具有一个相关的时隙控制电路，用于一次将一个比特的年龄和时隙提供给争用总线，从而确定有资格传输的最旧的数据包。竞争总线是异或线总线，其将时隙控制电路和控制缓冲器的输出电路互连，以输出包含最古老的数据分组的时隙号。在具有相同年龄的数据分组之间的联系的情况下，缓冲器的时隙号用于选择用于传输的数据分组。

80. 发明授权

US5323390A Multirate, sonet-ready, switching arrangement 失效
标题翻译：多速率，准备就绪，切换安排
公开(公告)号：US5323390A
公开(公告)日：1994-06-21
申请号：US964537
申请日：1992-10-20
申请人： Robert L. Pawelski
发明人： Robert L. Pawelski
IPC分类号： H04J3/00 , H04L7/00 , H04Q3/52 , H04Q11/04 , H04L12/54
CPC分类号： H04Q11/0407 , H04Q11/0478
摘要： A time-division multiplex switch (100) switches a hierarchy of data rates. It sets up higher-rate connections not as a plurality of individual lowest-rate connections but as one or more time slots in each one of a plurality of sequential frames (40,50) that correspond to that higher rate in each superframe (30). A time-slot-interchange switching element (131,141) of the switch utilizes a plurality of physically or logically distinct double-buffered data memories (301,302,303) each corresponding to a different one of the superframe and different-size ones of the frames. Reading and writing of each of the data memories' buffers alternates with the corresponding one of the superframe and different-size frames; reading of a data memory's buffer immediately follows writing of that buffer. Information from all incoming time slots is written into each one of the data memories, but only information corresponding to the data rate of an individual data memory's corresponding frame size is read from that data memory into outgoing time slots. A control memory (305) maps memory locations of the data memories to output time slots. A corresponding control architecture in a switching element ( 1700) of a time-multiplexed switch (120) uses a control memory (1701) that maps input ports to time slots of an output port.
摘要翻译：时分复用开关（100）切换数据速率的层次。它设置较高速率的连接，而不是多个单独的最低速率连接，而是作为与每个超帧（30）中的较高速率对应的多个连续帧（40,50）中的每一个中的一个或多个时隙，。交换机的时隙交换交换元件（131,141）利用多个物理或逻辑上不同的双缓冲数据存储器（301,302,303），每个双缓冲数据存储器对应于超帧和不同大小帧中的不同大小的数据存储器。每个数据存储器的缓冲器的读取和写入与超帧和不同大小的帧中的对应的一个交替; 在写入缓冲区之后立即读取数据存储器的缓冲区。来自所有输入时隙的信息被写入每个数据存储器中，但是仅将与数据存储器的相应帧大小的数据速率相对应的信息从该数据存储器读取到输出时隙。控制存储器（305）将数据存储器的存储器位置映射到输出时隙。时分复用交换机（120）的交换元件（1700）中的对应控制架构使用将输入端口映射到输出端口的时隙的控制存储器（1701）。

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