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    • 71. 发明授权
    • Method and system for decimating a pulse width modulated (PWM) signal
    • 用于抽取脉宽调制(PWM)信号的方法和系统
    • US07612696B2
    • 2009-11-03
    • US12057658
    • 2008-03-28
    • Poojan A. Wagh
    • Poojan A. Wagh
    • H03M5/08
    • H03H17/0283H03M1/504
    • A method and system of decimating a Pulse Width Modulated (PWM) signal (537) is provided. The method includes computing one or more timestamps (553) of the PWM signal (537), the PWM signal being at a first sample rate (567). The one or more timestamps (553) are computed at a second sample rate (568), which is lower than the first sample rate (567). Thereafter, the method generates a plurality of pre-filter signals (557-n) based on each of the one or more timestamps (553) and a plurality of translation factors (555-n). The plurality of pre-filter signals (557-n) is then filtered at the second sample rate (568) using a plurality of Infinite Impulse Response (IIR) filters (560-n) to generate a plurality of intermediate decimated Pulse Code Modulated (PCM) signals (563). The plurality of intermediate decimated PCM signals (563) is combined to generate a PCM signal (569).
    • 提供了抽取脉宽调制(PWM)信号(537)的方法和系统。 该方法包括计算PWM信号(537)的一个或多个时间戳(553),该PWM信号处于第一采样率(567)。 以比第一采样率(567)低的第二采样率(568)计算一个或多个时间戳(553)。 此后,该方法基于一个或多个时间戳(553)和多个平移因子(555-n)中的每个生成多个预滤波器信号(557-n)。 然后使用多个无限脉冲响应(II-N)滤波器(560-n),以第二采样率(568)对多个预滤波器信号(557-n)进行滤波,以产生多个中间抽取脉冲编码调制( PCM)信号(563)。 多个中间抽取PCM信号(563)被组合以产生PCM信号(569)。
    • 72. 发明授权
    • Apparatus for coordinating triggering of analog-to-digital conversions relative to pulse width modulation cycle timing
    • 用于协调相对于脉冲宽度调制周期定时的模数转换触发的装置
    • US07593500B2
    • 2009-09-22
    • US12049415
    • 2008-03-17
    • Bryan Kris
    • Bryan Kris
    • H03D3/24H03M5/08
    • H03K7/08
    • A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
    • 脉宽调制(PWM)发生器具有非常高的速度和高分辨率能力,能够产生标准互补PWM,推挽PWM,可变偏移PWM,多相PWM,限流PWM,电流复位PWM和独立时基PWM 同时进一步提供相对于PWM信号精确定时的模数转换(ADC)模块的自动触发。 应用包括控制开关电源,其需要非常高的速度操作以在高开关频率下获得高分辨率,以及改变驱动电源功率部件的PWM输出信号之间的相位关系的能力。 与更新多个占空比寄存器相比,可以使用单个PWM占空比寄存器来一次更新任何和/或所有PWM发生器,以减少数字处理器的工作负载。
    • 74. 发明授权
    • Method and system for increased effective resolution in an N-bit digital-to-analog converter
    • 用于在N位数模转换器中提高有效分辨率的方法和系统
    • US07061417B2
    • 2006-06-13
    • US10997105
    • 2004-11-24
    • Douglas Chin
    • Douglas Chin
    • H03M1/66H03M5/08H03K3/017H03K5/04H03K7/08
    • H03M1/822
    • In digital-to-analog conversion systems, a method and system for increased effective resolution in an N-bit DAC are provided. Additional resolution may be provided in an N-bit DAC by increasing the number of periods that an N-bit PWM may utilize to generate an output train of pulse widths with a desired duty cycle. An increased resolution bits parameter may correspond to the additional bits necessary to provide the increased resolution. An iterative process by which a desired value is converted into a sequence of N-bit control words may be based on a desired analog value and the increased resolution bits parameter. In addition to higher resolution, most of the output pulse AC energy is concentrated at the N-bit PWM basic frequency and above, allowing for simpler analog filtering of the pulse width modulated signal.
    • 在数模转换系统中,提供了一种用于提高N位DAC中有效分辨率的方法和系统。 可以通过增加N位PWM可以利用的周期数来产生具有期望占空比的脉冲宽度的输出序列,来在N位DAC中提供附加分辨率。 增加的分辨率位参数可以对应于提供增加的分辨率所必需的附加位。 期望值被转换成N位控制字序列的迭代过程可以基于期望的模拟值和增加的分辨率位参数。 除了更高的分辨率,大多数输出​​脉冲交流能量集中在N位PWM基频和以上,允许对脉宽调制信号进行更简单的模拟滤波。
    • 77. 发明申请
    • Decoder for decoding symmetric/asymmetric delay modulation signal and the method thereof
    • 用于解码对称/非对称延迟调制信号的解码器及其方法
    • US20050117668A1
    • 2005-06-02
    • US10986086
    • 2004-11-12
    • Cheng-Ming TangWen-Tsai Liao
    • Cheng-Ming TangWen-Tsai Liao
    • H03M5/08H04L7/00H04L25/49H04L25/493H04L27/10
    • H04L25/493H04L25/4906
    • The invention relates to a decoder for decoding a received signal to obtain a corresponding decoded bit series. The signal comprises a plurality of pulses. The decoder comprises a memory, a counting module, a transform module, and a logic module. The memory is for storing a predetermined look-up table; the look-up table comprises plural kinds of edge time duties and the corresponding decoded bit combinations thereof. The counting module is for measuring the edge time duty between high edges and low edges of adjacent pulses of the signal, so as to obtain a first and a second time series. The transform module, according to the look-up table, is for translating the first time series to a first decoded series, and the second time series to a second decoded series. The logic module is for performing a corresponding logic operation on the first and the second decoded series, so as to obtain the decoded bit series.
    • 本发明涉及一种用于对接收信号进行解码以获得对应的解码比特序列的解码器。 信号包括多个脉冲。 解码器包括存储器,计数模块,变换模块和逻辑模块。 存储器用于存储预定的查找表; 查找表包括多种边缘时间任务及其对应的解码比特组合。 计数模块用于测量信号的相邻脉冲的高边缘和低边缘之间的边沿时间占空比,以获得第一和第二时间序列。 根据查找表,变换模块用于将第一时间序列转换为第一解码序列,将第二时间序列转换为第二解码序列。 逻辑模块用于对第一和第二解码序列执行对应的逻辑运算,以获得解码的比特序列。
    • 80. 发明授权
    • Method and device for processing a received signal transmitting coded data
    • 用于处理发送编码数据的接收信号的方法和装置
    • US06873642B1
    • 2005-03-29
    • US09830516
    • 1999-10-13
    • Wolfgang FeyLing Chen
    • Wolfgang FeyLing Chen
    • B60T8/00H03M5/08H04L25/06H04L25/48H04L25/49H04L25/493H03D1/00
    • H04L25/493H04L25/069
    • The present invention relates to a method for conditioning a received signal that transmits coded data, wherein the coding of the data includes a defined coding clock pulse and the signal includes edges produced in accordance with the coding clock pulse, wherein from the received signal a time constant (tm) set in accordance with the coding clock pulse is determined, a first signal part which has a first edge is conditioned at a first time that is set in accordance with the time constant (tm) or in a first time window that is set in accordance with the time constant (tm), and a second signal part which has a second edge is conditioned at a second time that is set in accordance with the time constant (tm) and in dependence on the time of the first edge or in a second time window that is set in accordance with the time constant (tm) and in dependence on the time of the first edge.
    • 本发明涉及一种用于调节发送编码数据的接收信号的方法,其中数据的编码包括定义的编码时钟脉冲,并且该信号包括根据编码时钟脉冲产生的边缘,其中从接收信号中的时间 确定根据编码时钟脉冲设定的常数(tm),具有第一边缘的第一信号部分在根据时间常数(tm)设置的第一时间被调节,或者在第一时间窗口 根据时间常数(tm)设置,并且具有第二边缘的第二信号部分在根据时间常数(tm)设置的第二时间和根据第一边缘的时间或 在根据时间常数(tm)设定的第二时间窗口中,并且依赖于第一边缘的时间。