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    • 71. 发明授权
      US5393687A Method of making buried contact module with multiple poly si layers 失效
    • Method of making buried contact module with multiple poly si layers
    • 制作具有多个多晶硅层的埋地接触模块的方法
    • US5393687A
    • 1995-02-28
    • US167085
    • 1993-12-16
    • Mong-Song Liang
    • Mong-Song Liang
    • H01L21/285 , H01L21/265 , H01L21/225
    • H01L21/28525 , Y10S148/035
    • A new method of forming source/drain buried contact junctions is described. The method of forming a buried contact to a source/drain junction or other active device region in a silicon substrate is described. A first polysilicon layer is deposited over the surface of a silicon substrate. A second layer of polysilicon is deposited over the first layer of polysilicon wherein the polysilicon grain boundaries of the first and second polysilicon layers will be mismatched. The second polysilicon layer is doped. The grain boundary mismatch will slow the diffusion of the dopant into the silicon substrate. The dopant is driven in to form the buried contact with a shallow junction.
    • 描述了形成源极/漏极掩埋接触结的新方法。 描述了在硅衬底中形成与源极/漏极结或其它有源器件区的掩埋接触的方法。 第一多晶硅层沉积在硅衬底的表面上。 第二层多晶硅沉积在第一多晶硅层上，其中第一和第二多晶硅层的多晶硅晶界将被错配。 掺杂第二多晶硅层。 晶界失配将减缓掺杂剂向硅衬底的扩散。 掺杂剂被驱动以形成具有浅结的埋层接触。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 72. 发明授权
      US5275969A Semiconductor laser 失效
    • Semiconductor laser
    • 半导体激光器
    • US5275969A
    • 1994-01-04
    • US43835
    • 1993-04-07
    • Shogo Takahashi
    • Shogo Takahashi
    • H01L21/22 , H01L21/225 , H01S5/00 , H01L91/90
    • H01L21/2258 , Y10S148/035
    • A method for diffusing a P type impurity into a semiconductor includes the steps of selectively implanting ions of a first P type impurity into a semiconductor substrate and thermally diffusing a second P type impurity into the semiconductor substrate containing at least a region where the first P type impurity ions are implanted. Therefore, the diffusion speed of the P type impurity is increased in the ion implantation region, whereby the P type impurity diffusion region which almost corresponds to the ion implantation region can be obtained and P type diffusion can be performed in high concentration with high precision.
    • 将P型杂质扩散到半导体中的方法包括以下步骤：将第一P型杂质的离子选择性地注入到半导体衬底中，并将第二P型杂质热扩散到至少含有第一P型杂质的区域的半导体衬底中 杂质离子被植入。 因此，离子注入区域中P型杂质的扩散速度增加，能够得到与离子注入区域几乎相当的P型杂质扩散区域，能够高精度地进行P型扩散。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 74. 发明授权
      US4945070A Method of making cmos with shallow source and drain junctions 失效
    • Method of making cmos with shallow source and drain junctions
    • 制造具有浅源极和漏极结的cmos的方法
    • US4945070A
    • 1990-07-31
    • US301073
    • 1989-01-24
    • Sheng T. Hsu
    • Sheng T. Hsu
    • H01L21/225 , H01L21/336 , H01L21/8238 , H01L27/092
    • H01L29/66575 , H01L21/2257 , H01L21/823814 , H01L29/41783 , H01L27/0928 , Y10S148/035 , Y10S148/123
    • A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer. The silicide region over each of the well regions is doped with a conductivity modifier of a conductivity type opposite that of the well region. The device is then heated to diffuse the conductivity modifiers through the polycrystalline silicon layer into the silicon body to form shallow source and drain regions in each well at each side of the gate lines.
    • 具有浅源极和漏极区域的CMOS器件通过在主体中形成相邻导电类型的阱区而形成在具有主表面的单晶硅体中，该区具有从主表面延伸到主体中的绝缘材料的隔离区 沿着井区的交界处。 在每个阱区上的主表面上形成氧化硅薄层，并且在每个氧化硅层上形成导电多晶硅的栅极线。 栅极线的侧壁被一层氧化硅覆盖。 在每条栅极线的每一侧和栅极线上的主体表面上选择性地淀积一层多晶硅。 难熔金属层沉积在多晶硅层上。 多晶硅层被加热以使金属与硅反应并且至少部分地通过多晶硅层形成金属硅化物区域。 在每个阱区域之上的硅化物区域掺杂有导电类型与阱区域相反的导电性改性剂。 然后将该器件加热以将导电性改性剂通过多晶硅层扩散到硅体中，以在栅极线的每一侧的每个阱中形成浅的源极和漏极区域。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 78. 发明授权
      US4780425A Method of making a bipolar transistor with double diffused isolation regions 失效
    • Method of making a bipolar transistor with double diffused isolation regions
    • 制造具有双扩散隔离区域的双极晶体管的方法
    • US4780425A
    • 1988-10-25
    • US119668
    • 1987-11-12
    • Teruo Tabata
    • Teruo Tabata
    • H01L21/74 , H01L21/8222 , H01L21/8228 , H01L29/732 , H01L21/20 , H01L27/04
    • H01L29/7322 , H01L21/74 , H01L21/8222 , H01L21/82285 , Y10S148/011 , Y10S148/035 , Y10S148/038
    • The present invention relates to a semiconductor device and a method of producing the same. According to this method, a lower diffusion layer of a double isolation diffusion area is attached to a surface of a substrate, an epitaxial layer being formed on the lower diffusion layer, the lower diffusion layer being largely outdiffused upwardly in the epitaxial layer and simultaneously an element diffusion area being deeply diffused from a surface of the epitaxial layer, and then an upper diffusion layer of the double isolation diffusion area being shallowly diffused from the surface of the epitaxial layer. Thus, the lateral expansion of the upper diffusion layer of the double isolation diffusion area can be suppressed and the integrated extent can be improved. On the other hand, in a semiconductor device of the present invention, the above described double isolation diffusion area is formed and a collector area, a base area and an emitter area are formed all over the width of the epitaxial layer (the base area and the emitter area are formed by a double diffusion). In addition, it includes a vertical type transistor whose fluctuation of a width of the base area is reduced, so that the transition frequency f.sub.T and current gain h.sub.FE of this transistor are increased.
    • 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 根据该方法，将双重隔离扩散区域的下部扩散层附着在基板的表面，外延层形成在下部扩散层上，下部扩散层在外延层中大大向外扩散，同时 元件扩散区域从外延层的表面深度扩散，然后双重隔离扩散区域的上扩散层从外延层的表面浅扩散。 因此，可以抑制双重隔离扩散区域的上扩散层的横向膨胀，并且可以提高一体化程度。 另一方面，在本发明的半导体装置中，形成上述双重隔离扩散区域，并且在外延层的整个宽度（基底面积和宽度）上形成集电极区域，基极区域和发射极区域 发射极区域由双扩散形成）。 此外，它包括垂直型晶体管，其基极区域的宽度的波动减小，使得该晶体管的跃迁频率fT和电流增益hFE增加。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 79. 发明授权
      US3909119A Guarded planar PN junction semiconductor device 失效
    • Guarded planar PN junction semiconductor device
    • 保护的平面PN结半导体器件
    • US3909119A
    • 1975-09-30
    • US44020374
    • 1974-02-06
    • WESTINGHOUSE ELECTRIC CORP
    • WOLLEY ELDEN D
    • H01L29/73 , H01L21/331 , H01L29/00 , H01L29/06 , H01L29/732 , H01L29/74 , H01L29/861 , H01L29/90 , H01L29/34
    • H01L29/861 , H01L29/00 , H01L29/0626 , H01L29/0688 , H01L29/7322 , Y10S148/035 , Y10S148/049 , Y10S148/05 , Y10S148/085 , Y10S148/145 , Y10S257/913
    • A semiconductor device with at least one planar PN junction is provided in a semiconductor body having at least one major surface. The body has first and second impurity regions of opposite conductivity type forming a first PN junction therebetween. The first impurity region is positioned adjoining the major surface, and the second impurity region is positioned in interior portions of the body adjoining the first impurity region. The second impurity region has an impurity concentration profile and thickness to support a space-charge region on application of a given reverse bias voltage across the PN junction. A third impurity region is positioned in the semiconductor body adjoining the major surface around the first impurity region, and at least laterally encompassing the first and second impurity regions to form a second PN junction with the first impurity region, said second PN junction extending contiguously around the first PN junction and adjoining the major surface around and spaced from the second impurity region. The third impurity region has an impurity concentration profile and thickness to more than support the space-charge region formed at the second PN junction on application of said reverse bias voltage across the PN junction so that the blocking voltage of the device can be controlled by the avalanche breakdown and punch-through voltage at the second impurity region. For high voltage applications, field limiting rings can be positioned in the semiconductor body adjoining the major surface around and spaced from the second PN junction to form additional PN junctions with the third impurity region and to divide the electric field on application of a given applied voltage.
    • 具有至少一个平面PN结的半导体器件设置在具有至少一个主表面的半导体本体中。 主体具有相反导电类型的第一和第二杂质区域，在其间形成第一PN结。 第一杂质区位于与主表面相邻的位置，第二杂质区位于与第一杂质区相邻的本体的内部。 第二杂质区域具有杂质浓度分布和厚度以在通过PN结施加给定的反向偏置电压时支持空间电荷区域。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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