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1. 发明授权

US5439848A Method for fabricating a self-aligned multi-level interconnect 失效
标题翻译：制造自对准多层互连的方法
公开(公告)号：US5439848A
公开(公告)日：1995-08-08
申请号：US997730
申请日：1992-12-30
申请人： Sheng T. Hsu , Robert G. Pollachek
发明人： Sheng T. Hsu , Robert G. Pollachek
IPC分类号： H01L21/768 , H01L21/8244 , H01L23/528 , H01L23/532 , H01L27/11
CPC分类号： H01L23/53271 , H01L21/76805 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.
摘要翻译：公开了一种自对准多电平互连结构及其制造方法。多级互连结构通过以下步骤制造：（1）形成第一多个间隔开的绝缘层[231-233]，其中第一多个包括顶部绝缘层[233]; （2）形成第二多个间隔开的导体[221,222]并将它们指向定位在绝缘层之间; （3）限定延伸穿过顶部绝缘层[233]的第一孔[233h]。（4）使用第一孔[233h]通过下面的导体和绝缘层限定一连串的自对准随后的孔[222h，232h，22ih，231h]，每个连续的孔与上面的一个连续并自对准它; 和（5）限定延伸穿过一连串的自对准孔的贯通导体[223]。在多层SRAM单元中采用自对准多级互连结构。

2. 发明授权

US4797721A Radiation hardened semiconductor device and method of making the same 失效
标题翻译：辐射硬化半导体器件及其制造方法
公开(公告)号：US4797721A
公开(公告)日：1989-01-10
申请号：US37482
申请日：1987-04-13
申请人： Sheng T. Hsu
发明人： Sheng T. Hsu
IPC分类号： H01L29/08 , H01L29/786 , H01L27/12 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/78609
摘要： An N-channel transistor formed in a layer of semiconductor material disposed on a insulating substrate is disclosed. The source region has a depth less than the thickness of the semiconductor layer so that a P-type region can be formed in the semiconductor layer between the source region and the insulating substrate. This P-type region has an impurity concentration sufficient to prevent the depletion region of the source from extending to the interface between the layer of semiconductor material and the substrate. The P-type region substantially prevents back-channel leakage currents from flowing between the source region and the drain region along the portion of the layer of semiconductor material immediately adjacent the insulating substrate when the device has been irradiated.
摘要翻译：公开了一种形成在设置在绝缘基板上的半导体材料层中的N沟道晶体管。源极区域的深度小于半导体层的厚度，从而可以在源极区域和绝缘基板之间的半导体层中形成P型区域。该P型区域具有足以防止源极的耗尽区域延伸到半导体材料层与衬底之间的界面的杂质浓度。 P型区域基本上防止了背光通道泄漏电流沿着紧邻绝缘基板的半导体材料层的部分在源极区域和漏极区域之间流动，当器件被照射时。

3. 发明授权

US4637836A Profile control of boron implant 失效
标题翻译：硼植入物的轮廓控制
公开(公告)号：US4637836A
公开(公告)日：1987-01-20
申请号：US778986
申请日：1985-09-23
申请人： Doris W. Flatley , Sheng T. Hsu
发明人： Doris W. Flatley , Sheng T. Hsu
IPC分类号： H01L27/092 , H01L21/265 , H01L21/3215 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L21/26
CPC分类号： H01L21/823828 , H01L21/32155 , H01L21/823857 , Y10S438/919
摘要： The ion implantation of a silicon structure isolated from a semiconductor substrate by a layer of silicon dioxide with boron ions to render it p type conductive is improved by initially doping the silicon with phosphorus ions. The presence of the phosphorus ions in the silicon prevents the implanted boron ions from rapidly migrating into the silicon dioxide during annealing.
摘要翻译：通过用磷离子初始掺杂硅，改善了通过具有硼离子的二氧化硅层与半导体衬底隔离以形成p型导电的硅结构的离子注入。在硅中存在磷离子防止注入的硼离子在退火过程中迅速迁移到二氧化硅中。

4. 发明授权

US4519126A Method of fabricating high speed CMOS devices 失效
标题翻译：制造高速CMOS器件的方法
公开(公告)号：US4519126A
公开(公告)日：1985-05-28
申请号：US560459
申请日：1983-12-12
申请人： Sheng T. Hsu
发明人： Sheng T. Hsu
IPC分类号： H01L21/768 , H01L21/8238 , H01L21/283
CPC分类号： H01L21/76889 , H01L21/823835
摘要： In order to reduce the mechanical stress that occurs at the interface of a layer of a refractory metal silicide and a layer of silicon dioxide, it is proposed that a buffer layer of polycrystalline silicon be interposed between the two layers. To accomplish this and prior to forming contact openings, the buffer layer of polycrystalline silicon is deposited on the layer of silicon dioxide and the structure is then provided with an apertured mask to define the contact openings. The structure is then initially etched through both the buffer layer and the underlying layer of silicon dioxide in order to expose portions of the buried contact regions followed by a second etch of only the buffer layer to only expose portions of the layer of silicon dioxide in order to form a gate member and any required interconnects. The process further includes the formation of a layer of metal silicide on the interconnects, in the contact openings and on the gate member.
摘要翻译：为了减少在难熔金属硅化物层和二氧化硅层的界面处发生的机械应力，提出在两层之间插入多晶硅缓冲层。为了在形成接触开口之前和之前形成接触开口，多晶硅的缓冲层沉积在二氧化硅层上，然后该结构设置有多孔掩模以限定接触开口。然后，首先通过缓冲层和二氧化硅的下层蚀刻该结构，以便暴露部分埋藏的接触区域，然后仅对缓冲层进行第二次蚀刻，以仅依次暴露部分二氧化硅层以形成门构件和任何所需的互连。该方法还包括在互连件上，接触开口中和栅极部件上形成金属硅化物层。

5. 发明授权

US4349584A Process for tapering openings in ternary glass coatings 失效
标题翻译：三元玻璃涂层开口渐缩的工艺
公开(公告)号：US4349584A
公开(公告)日：1982-09-14
申请号：US258431
申请日：1981-04-28
申请人： Doris W. Flatley , Sheng T. Hsu
发明人： Doris W. Flatley , Sheng T. Hsu
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3105 , H01L21/316
CPC分类号： H01L21/3105 , Y10S438/978
摘要： A process for defining improved tapered openings in glass coatings requires that passivating layers be formed of a doped silicon oxide having a relatively low flow temperature formed on a layer of undoped silicon oxide. After the contact openings are formed, both oxide layers are heated to a temperature below the flow temperature of the doped layer for a period of time sufficient to only soften and partially reflow the doped layer, the temperature being insufficient to form a significant oxide growth on the exposed portion of the semiconductor body.
摘要翻译：用于在玻璃涂层中限定改进的锥形开口的方法要求钝化层由形成在未掺杂的氧化硅层上的相对低的流动温度的掺杂氧化硅形成。在形成接触开口之后，将两个氧化物层加热到低于掺杂层的流动温度的温度一段足以仅使软化并部分回流掺杂层的时间，该温度不足以形成显着的氧化物生长半导体本体的暴露部分。

6. 发明授权

US4295266A Method of manufacturing bulk CMOS integrated circuits 失效
标题翻译：批量CMOS集成电路的制造方法
公开(公告)号：US4295266A
公开(公告)日：1981-10-20
申请号：US164681
申请日：1980-06-30
申请人： Sheng T. Hsu
发明人： Sheng T. Hsu
IPC分类号： H01L27/092 , H01L21/027 , H01L21/033 , H01L21/316 , H01L21/762 , H01L21/8238 , H01L29/78 , H01L21/26
CPC分类号： H01L21/76208 , H01L21/0271 , H01L21/033 , H01L21/8238 , Y10S438/92
摘要： The method presented may be utilized in manufacturing CMOS integrated circuits either in an isoplanar or in a LOCOS process. The method entails the simultaneous formation of the well region with the oxide isolation regions by a drive-in diffusion which is conducted in a dry oxygen ambient. The utilization of the process insures that compounds of silicon, nitrogen and oxygen will not be present in the bulk silicon where they can effect the quality of gate oxides which are subsequently formed.
摘要翻译：所提出的方法可以用于在等面或LOCOS工艺中制造CMOS集成电路。该方法需要通过在干氧环境中进行的驱入扩散同时形成具有氧化物隔离区的阱区。该方法的利用确保硅，氮和氧的化合物不会存在于体硅中，在这些硅中它们可以影响随后形成的栅极氧化物的质量。

7. 发明授权

US4249095A Comparator, sense amplifier 失效
标题翻译：比较器，读出放大器
公开(公告)号：US4249095A
公开(公告)日：1981-02-03
申请号：US15247
申请日：1979-02-26
申请人： Sheng T. Hsu
发明人： Sheng T. Hsu
IPC分类号： G11C7/06 , H03K5/02 , H03K17/56 , H03F3/45
CPC分类号： H03K5/023 , G11C7/062
摘要： A voltage comparator utilizing complementary MOS techniques. The comparator includes a pair of complementary field effect transistors with serial connected channels. A first signal to be compared is applied to the gate of one of the pair of transistors. A second signal is applied to the gate of the pair of transistors such that the transistor pair operates as a quasi-differential amplifier. The output of the transistor pair is subsequently amplified by a cross-coupled latch.
摘要翻译：一种利用互补MOS技术的电压比较器。比较器包括一对具有串行连接通道的互补场效应晶体管。要比较的第一信号被施加到该对晶体管之一的栅极。第二信号被施加到该对晶体管的栅极，使得晶体管对作为准差分放大器工作。晶体管对的输出随后被交叉耦合的锁存放大。

8. 发明授权

US4247861A High performance electrically alterable read-only memory (EAROM) 失效
标题翻译：高性能电可变只读存储器（EAROM）
公开(公告)号：US4247861A
公开(公告)日：1981-01-27
申请号：US018859
申请日：1979-03-09
申请人： Sheng T. Hsu , Richard J. Hollingsworth
发明人： Sheng T. Hsu , Richard J. Hollingsworth
IPC分类号： G11C16/04 , H01L27/07 , H01L29/792 , H01L27/02 , G11C11/34 , H01L29/34 , H03K5/00
CPC分类号： H01L27/0716 , G11C16/0466 , H01L29/792
摘要： The invention is a memory device which includes a metal-nitride-oxide semiconductor (MNOS) insulated gate field effect transistor (IGFET) which is built in series with the base of a bipolar transistor to provide both bipolar current handling capability and bipolar radiation hardness while retaining MNOS memory performance.
摘要翻译：本发明是一种存储器件，其包括与双极晶体管的基极串联构成的金属氮化物 - 氧化物半导体（MNOS）绝缘栅场效应晶体管（IGFET），以提供双极电流处理能力和双极辐射硬度，保留MNOS内存性能。

9. 发明授权

US5468657A Nitridation of SIMOX buried oxide 失效
标题翻译： SIMOX掩埋氧化物的氮化
公开(公告)号：US5468657A
公开(公告)日：1995-11-21
申请号：US261443
申请日：1994-06-17
申请人： Sheng T. Hsu
发明人： Sheng T. Hsu
IPC分类号： H01L21/02 , H01L21/265 , H01L21/762 , H01L27/00 , H01L27/12 , H01L21/76
CPC分类号： H01L21/26533 , H01L21/76243 , Y10S438/98
摘要： A method is provided for improving the electrical isolation between surface regions and underlying support regions in SIMOX buried oxide wafers. The method implants nitrogen ions into a wafer to approximately the same depth as oxygen ions are implanted during SIMOX processing. A subsequent heating step causes the nitrogen ions to migrate to the interface region between the buried oxide and the upper and lower semiconductor regions of the substrate. The nitrogen passivates the interface regions to reduce the presence of buried free electrons trapped in the substrate. Nitrogen implantation can be performed before, during, or after the oxygen is implanted. Nitrogen ions can also be implanted after the SIMOX buried silicon dioxide layer has been formed. If the latter alternative is followed, the wafer must be subsequently heated to migrate the nitrogen ions to the interface regions within the substrate. Such subsequent heating can be performed as part of the formation of devices on the substrate. The resultant nitrogen passivated SIMOX substrate has improved electrical isolation between surface active devices and the supporting substrate. The invention also yields a substantial increase in the breakdown voltage of the buried oxide layer.
摘要翻译：提供了一种改进SIMOX掩埋氧化物晶片中表面区域和下面的支撑区域之间的电气隔离的方法。该方法将氮离子注入到晶片中，以在SIMOX处理期间植入氧离子大致相同的深度。随后的加热步骤使氮离子迁移到掩埋氧化物和衬底的上半导体区域和下半导体区域之间的界面区域。氮钝化界面区域以减少被俘获在衬底中的掩埋自由电子的存在。可以在植入氧气之前，之中或之后进行氮注入。在形成SIMOX埋二氧化硅层之后，也可以注入氮离子。如果遵循后一种选择，则必须随后加热晶片以将氮离子迁移到衬底内的界面区域。这样的后续加热可以作为在基板上形成器件的一部分来执行。所得的氮钝化SIMOX衬底具有改善表面活性器件和支撑衬底之间的电隔离。本发明还导致掩埋氧化物层的击穿电压显着增加。

10. 发明授权

US5089429A Self-aligned emitter BiCMOS process 失效
标题翻译：自对准发射器BICMOS过程
公开(公告)号：US5089429A
公开(公告)日：1992-02-18
申请号：US370413
申请日：1989-06-22
申请人： Sheng T. Hsu
发明人： Sheng T. Hsu
IPC分类号： H01L21/331 , H01L21/8249
CPC分类号： H01L29/66272 , H01L21/8249
摘要： A process is disclosed for forming bipolar transistors in a BiCMOS process which is fully compatible with the CMOS process used to form other devices in the same integrated circuit. The process produces bipolar transistor sizes which are compatible with the minimum size features and design rules of the CMOS process. A CVD silicon oxide layer to be used to form spacers is deposited on the top of emitter and gate electrodes covered with a first oxide layer.
摘要翻译：公开了一种用于在BiCMOS工艺中形成双极晶体管的工艺，其与用于在同一集成电路中形成其它器件的CMOS工艺完全兼容。该过程产生与CMOS工艺的最小尺寸特征和设计规则兼容的双极晶体管尺寸。用于形成间隔物的CVD氧化硅层沉积在被第一氧化物层覆盖的发射极和栅电极的顶部上。

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