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71. 发明申请

US20130146220A1 METHOD OF MANUFACTURING WIRING SUBSTRATE 有权
标题翻译：制造接线基板的方法
公开(公告)号：US20130146220A1
公开(公告)日：2013-06-13
申请号：US13762791
申请日：2013-02-08
申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.
发明人： Tatsuya Nakamura , Tomoko Yamada
IPC分类号： H05K3/46
CPC分类号： H05K3/46 , H05K3/0097 , H05K3/025 , H05K3/108 , H05K3/4652 , H05K3/4682 , H05K2201/09509 , H05K2201/096 , H05K2203/0152 , H05K2203/1536 , Y10T156/11 , Y10T156/1195
摘要： Two stacked bodies, each having a metal layer provided on a first metallic foil with carrier via a first insulating layer, are prepared. The first metallic foil with carrier has a metallic foil provided on a carrier plate via a peeling layer. A joined body is formed by jointing the stacked bodies such that the carrier plates are joined via a joining layer. First conductor patterns are formed by patterning the metal layers on both sides of the joined body. Second metallic foils with carrier are provided to the first conductor patterns of the joined body such that the first conductor patterns are opposed to the metallic foils via second insulating layers. Two substrates are formed by peeling the carrier plates with carrier from the peeling layers. Second conductor patterns which are connected electrically to the first conductor patterns are formed from the metallic foils of the substrate.
摘要翻译：准备两个层叠体，每个层叠体通过第一绝缘层具有设置在具有载体的第一金属箔上的金属层。具有载体的第一金属箔具有通过剥离层设置在载体板上的金属箔。通过接合层叠体形成接合体，使得承载板通过接合层接合。第一导体图案通过在接合体的两侧上构图金属层而形成。具有载体的第二金属箔被提供到接合体的第一导体图案，使得第一导体图案经由第二绝缘层与金属箔相对。通过用载体从剥离层剥离载体板来形成两个基板。与第一导体图案电连接的第二导体图案由基板的金属箔形成。

72. 发明申请

US20130057372A1 COILED MAGNETIC RING 失效
标题翻译：卷绕磁环
公开(公告)号：US20130057372A1
公开(公告)日：2013-03-07
申请号：US13604110
申请日：2012-09-05
申请人： Philippe Klein
发明人： Philippe Klein
IPC分类号： H01F5/02
CPC分类号： H05K1/165 , G01R33/0052 , H01F27/2804 , H01F2027/2809 , H05K3/46 , H05K2201/086 , H05K2201/09063 , H05K2201/09263 , H05K2201/09672 , H05K2201/097
摘要： This magnetic ring is formed by an upper U-shaped part and a lower U-shaped part, each upper and lower part comprising two vertical arms each introduced into a respective hole of the printed circuit board, each arm of the upper part being superimposed, within the respective hole and in a horizontal direction, on the corresponding arm of the lower part to set up magnetic continuity between these two parts of the magnetic ring.
摘要翻译：该磁环由上部U形部分和下部U形部分形成，每个上部和下部部分包括两个垂直臂，每个引导到印刷电路板的相应孔中，上部的每个臂都叠加着，在相应的孔中并且在水平方向上在下部的相应臂上，以在磁环的这两个部分之间建立磁性连续性。

73. 发明授权

US08168891B1 Differential trace profile for printed circuit boards 有权
公开(公告)号：US08168891B1
公开(公告)日：2012-05-01
申请号：US12151088
申请日：2008-05-02
申请人： Joel R. Goergen , Yi Zheng
发明人： Joel R. Goergen , Yi Zheng
IPC分类号： H05K1/00
CPC分类号： H05K1/0216 , B32B2305/076 , B32B2309/08 , B32B2457/08 , H01P3/081 , H05K1/024 , H05K1/0242 , H05K1/0245 , H05K1/0298 , H05K1/0366 , H05K3/0091 , H05K3/46 , H05K3/4611 , H05K2201/0187 , H05K2201/029 , H05K2201/09236 , H05K2201/09745 , H05K2201/098 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49156 , Y10T29/49165
摘要： Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

74. 发明申请

US20120037409A1 METHOD OF MANUFACTURING MULTILAYER PRINTED WIRING BOARD AND MULTILAYER WIRING BOARD OBTAINED THEREBY 有权
标题翻译：制造多层印刷线路板和多层布线板的方法
公开(公告)号：US20120037409A1
公开(公告)日：2012-02-16
申请号：US13256114
申请日：2010-03-09
申请人： Norihiro Yamaguchi , Hiroaki Umeda , Ken Yukawa
发明人： Norihiro Yamaguchi , Hiroaki Umeda , Ken Yukawa
IPC分类号： H05K1/09 , H05K3/30
CPC分类号： H05K3/46 , H01B1/22 , H05K1/0298 , H05K1/095 , H05K3/0032 , H05K3/4069 , H05K3/462 , H05K2201/0191 , H05K2201/0272 , H05K2201/0355 , H05K2201/10378 , H05K2203/0278 , H05K2203/0425 , H05K2203/1105 , H05K2203/111 , H05K2203/1194 , H05K2203/1461 , H05K2203/1572 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49165
摘要： In a method of manufacturing a multilayer board, including: a drilling step for forming a via hole through a pre-preg by laser beam machining, a step of filling the via hole with conductive paste containing a resin component and metal powder, and a step of arranging copper layers or copper layer portions of patterned boards on and under the filled conductive paste and pressing the same, a multilayer printed wiring board superior in conductivity and long-term stability is obtained by using alloying paste as the conductive paste in which at least part of the metal powder is melted and the metal powders adjacent to each other are alloyed, using a pre-preg having a ratio A/B of at least 10 before subjected to preheating, where A is a storage modulus at an inflection point where the storage modulus changes from increasing to decreasing and B is a storage modulus at an inflection point where the storage modulus changes from decreasing to increasing in a temperature profile rising from 60° C. to 200° C., and preheating the pre-preg before the drilling step to reduce the ratio A/B to below 10.
摘要翻译：在制造多层板的方法中，包括：通过激光束加工形成通孔的钻孔步骤，用含有树脂成分和金属粉末的导电膏填充通孔的步骤，以及步骤在填充的导电糊料上和下方布置图案化板的铜层或铜层部分并对其进行压制，通过使用合金糊作为导电浆料，获得导电性和长期稳定性优异的多层印刷线路板，其中至少使用在进行预热之前，使用比例A / B为10以上的预浸料，将金属粉末的一部分熔融并且彼此相邻的金属粉末合金化，其中A是在拐点处的储能模量，储能模量从增加到减少变化，B是在从60℃升高的温度分布中储能模量从降低到升高的拐点处的储能模量到200℃，并且在钻井步骤之前预热预浸料以将A / B比率降低到10以下。

75. 发明授权

US08072769B2 Component-embedded module and manufacturing method thereof 有权
标题翻译：组件嵌入式模块及其制造方法
公开(公告)号：US08072769B2
公开(公告)日：2011-12-06
申请号：US12579617
申请日：2009-10-15
申请人： Tsutomu Ieki , Kazuyuki Yuda
发明人： Tsutomu Ieki , Kazuyuki Yuda
IPC分类号： H05K1/18
CPC分类号： H05K1/141 , H01L23/552 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/15313 , H01L2924/19105 , H05K1/0218 , H05K1/183 , H05K1/187 , H05K3/007 , H05K3/20 , H05K3/284 , H05K3/303 , H05K3/46 , H05K3/4694 , H05K3/4697 , H05K2201/0715 , H05K2201/0979 , H05K2201/09972 , H05K2203/016 , H05K2203/167 , Y10T29/4913 , H01L2224/0401
摘要： A component-embedded module includes a module substrate having wiring electrodes on the upper surface thereof, first circuit components mounted on the wiring electrodes, a sub-module disposed on an area on which no wiring electrodes are provided, and an insulating resin layer provided on substantially the entire upper surface of the module substrate such that the insulating resin layer covers at least a portion of the first circuit components and sub-module. The second circuit components including an integrated circuit element are mounted on the sub-module or embedded therein. Via conductors are provided through the module substrate from the lower surface thereof and are directly coupled to terminal electrodes on the lower surface of the sub-module. By using a substrate having a wiring greater accuracy than that of the module substrate, a reliable component-embedded module is obtained.
摘要翻译：组件嵌入式模块包括在其上表面上具有布线电极的模块基板，安装在布线电极上的第一电路部件，设置在不设有布线电极的区域上的子模块以及设置在其上的绝缘树脂层基本上整个模块基板的上表面，使得绝缘树脂层覆盖第一电路部件和子模块的至少一部分。包括集成电路元件的第二电路部件安装在子模块上或嵌入其中。通孔导体通过模块基板从其下表面提供，并且直接耦合到子模块的下表面上的端子电极。通过使用具有比模块基板的布线精度更高的布线的基板，获得了可靠的部件嵌入式模块。

76. 发明申请

US20110204911A1 PROBER UNIT 失效
标题翻译：探索单位
公开(公告)号：US20110204911A1
公开(公告)日：2011-08-25
申请号：US12712734
申请日：2010-02-25
申请人： Gunsei KIMOTO
发明人： Gunsei KIMOTO
IPC分类号： G01R31/02
CPC分类号： G01R31/2886 , G01R1/06727 , H05K1/0268 , H05K1/11 , H05K1/144 , H05K3/46 , H05K2201/041 , H05K2201/09472 , H05K2201/096 , H05K2201/09709
摘要： To facilitate connection between a narrow-pitched probe assembly and a coarse-pitched printed circuit board. A prober unit in which probes are brought into contact with to-be-tested semiconductor chips to establish electrical connection between the semiconductor chips and a test unit via the probes, in which: a probe assembly and a plurality of wiring boards are prepared, the probe assembly including output terminals to be connected directly to the probes, the probe assembly being constituted by integrated regularly-arranged multiple probe groups including the output terminals, and each of the wiring boards including wiring adhering to a surface of a non-conductive film; and an n-th row of an output terminal group of the probe assembly is brought into contact with a land group provided at an end of an n-th wiring board, and a wiring terminal provided at the other end of the n-th wiring board is connected to one of a wiring board of the test unit and a connector to establish electrical connection between the to-be-tested semiconductor chips and the test unit.
摘要翻译：为了便于窄间距探针组件和粗调印刷电路板之间的连接。探针单元，其中探针与待测试的半导体芯片接触，以通过探针在半导体芯片和测试单元之间建立电连接，其中：准备探针组件和多个布线板，探针组件，其包括要直接连接到探针的输出端子，探针组件由包括输出端的集成的规则排列的多个探针组构成，并且每个布线板包括附着在非导电膜表面上的布线; 并且探针组件的输出端子组的第n行与设置在第n布线板的端部的平台组接触，并且设置在第n布线的另一端的布线端子板连接到测试单元的布线板之一和连接器，以在待测半导体芯片和测试单元之间建立电连接。

77. 发明申请

US20110088842A1 DIFFERENTIAL TRACE PROFILE FOR PRINTED CIRCUIT BOARDS 有权
标题翻译：印刷电路板的差分跟踪曲线
公开(公告)号：US20110088842A1
公开(公告)日：2011-04-21
申请号：US12961610
申请日：2010-12-07
申请人： JOEL R. GOERGEN , Yi Zheng
发明人： JOEL R. GOERGEN , Yi Zheng
IPC分类号： B32B37/04
CPC分类号： H05K1/0216 , B32B2305/076 , B32B2309/08 , B32B2457/08 , H01P3/081 , H05K1/024 , H05K1/0242 , H05K1/0245 , H05K1/0298 , H05K1/0366 , H05K3/0091 , H05K3/46 , H05K3/4611 , H05K2201/0187 , H05K2201/029 , H05K2201/09236 , H05K2201/09745 , H05K2201/098 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49156 , Y10T29/49165
摘要： Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.
摘要翻译：公开了电路板及其制造方法。电路板使用形成为包括纵向通道的导体承载高速信号。通道增加了导体的表面积，从而增强了导体承载高速信号的能力。在至少一些实施例中，通道内的介电常数和通道之外的介质常数之间也存在不连续性，这被认为可减少信号损耗。

78. 发明授权

US07648821B2 Method of forming flexible electronic circuits 有权
标题翻译：形成柔性电子电路的方法
公开(公告)号：US07648821B2
公开(公告)日：2010-01-19
申请号：US11911825
申请日：2006-03-24
申请人： Sean D. Slater , John R. Fyson , Christopher B. Rider , David T. Clarke , Jurjen F. Winkel , Peter Hewitson
发明人： Sean D. Slater , John R. Fyson , Christopher B. Rider , David T. Clarke , Jurjen F. Winkel , Peter Hewitson
IPC分类号： G03C5/18 , G03C5/26 , G03C1/08
CPC分类号： G03C5/58 , H05K3/106 , H05K3/46 , Y10T428/24917
摘要： A multiple layer photosensitive element having at least three differently sensitised photosensitive layers on one side of a support, such as a, transparent flexible support, is imagewise exposed according to a desired circuit pattern and developed to form two layers of conductive track patterns from each photosensitive layer, which may then be connected together by forming vias by drilling or in situ generation. The resulting multiple layer conductive element has application in the field of printed circuit board manufacture or as the backplane electronic element of a flexible display device.
摘要翻译：在诸如透明柔性支撑体的支撑体的一侧上具有至少三个不同敏化感光层的多层感光元件根据期望的电路图案成像曝光并显影以形成来自每个感光体的两层导电迹线图案层，然后可以通过钻孔或原位生成形成通孔来连接在一起。所得到的多层导电元件可用于印刷电路板制造领域或作为柔性显示装置的背板电子元件。

79. 发明申请

US20090284275A1 CONDUCTIVE FILM STRUCTURE, FABRICATION METHOD THEREOF, AND CONDUCTIVE FILM TYPE PROBE DEVICE FOR IC 有权
标题翻译：导电膜结构及其制造方法及IC导电膜型探针装置
公开(公告)号：US20090284275A1
公开(公告)日：2009-11-19
申请号：US12323422
申请日：2008-11-25
申请人： Min-Chieh Chou , Tung-Chuan Wu , Jen-Hui Tsai , Hung-Yi Lin
发明人： Min-Chieh Chou , Tung-Chuan Wu , Jen-Hui Tsai , Hung-Yi Lin
IPC分类号： G01R1/073 , G01R3/00 , H01B5/14
CPC分类号： G01R1/06755 , G01R1/06733 , G01R3/00 , H05K1/028 , H05K1/118 , H05K3/46 , H05K2201/0397 , H05K2201/051 , H05K2201/055 , Y10T29/49124 , Y10T29/49155
摘要： A method for forming a conductive film structure is provided, which includes providing a flexible insulating substrate, forming a conductive film overlying the flexible insulating substrate, patterning the conductive film to form a plurality of micro-wires overlying the flexible insulating substrate, wherein the micro-wires are extended substantially parallel to each other, forming an insulating layer overlying the flexible insulating substrate and the micro-wires, and winding or folding the flexible insulating substrate along an axis substantially parallel to an extending direction of the micro-wires to form a conducting lump.
摘要翻译：提供了一种形成导电膜结构的方法，其包括提供柔性绝缘基板，形成覆盖柔性绝缘基板的导电膜，图案化导电膜以形成覆盖柔性绝缘基板的多条微细线，其中微型电线基本上彼此平行地延伸，形成覆盖柔性绝缘基板和微线的绝缘层，以及沿着基本上平行于微线的延伸方向的轴线缠绕或折叠柔性绝缘基板，以形成导致肿块

80. 发明授权

US07205655B2 Multilayer circuit including stacked layers of insulating material and conductive sections 失效
标题翻译：多层电路包括堆叠的绝缘材料层和导电部分
公开(公告)号：US07205655B2
公开(公告)日：2007-04-17
申请号：US10806269
申请日：2004-03-23
申请人： Mika Sippola
发明人： Mika Sippola
IPC分类号： H01L23/12
CPC分类号： H05K3/46 , H01F17/0013 , H01F27/2804 , H01F27/2847 , H01F41/041 , H01F2027/2861 , H05K1/118 , H05K1/165 , H05K3/4084 , H05K3/4092 , H05K2201/0379 , H05K2201/0394 , H05K2201/0397 , H05K2201/055
摘要： The invention relates to the manufacturing of a multilayer structure and especially it relates to the manufacturing of a three-dimensional structure and its use as an electronics assembly substrate and as a winding for transformers and inductors. When a multilayer structure is manufactured by folding a conductor-insulator-conductor laminate, where the conductor layers to be separated from each other follow each other on opposite sides of the conductor-insulator-conductor laminate in the sections following each other and where the insulator has been removed from the places where the conductor layers are to be connected together after folding, it is possible to manufacture a wide range of three-dimensional multilayer structures where the volume occupied by the windings over the total volume can be maximized. Alternatively, by using the method it is also possible to manufacture a multilayer structure where components have been buried inside. The method makes it also possible to make connections between layers in a flexible manner. Among other issues, the method can be easily automated for mass-production.
摘要翻译：本发明涉及多层结构的制造，特别涉及三维结构的制造及其作为电子组装基板和用于变压器和电感器的绕组的用途。当通过折叠导体 - 绝缘体 - 导体层叠体来制造多层结构时，彼此分离的导体层在彼此相邻的部分中的导体 - 绝缘体 - 导体层叠体的相对侧彼此相对，并且绝缘体已经从折叠后导体层要连接在一起的地方去除，可以制造宽范围的三维多层结构，其中绕组占用的体积可以最大化。或者，通过使用该方法，也可以制造其中已经将部件埋入其中的多层结构。该方法还可以以灵活的方式在层之间进行连接。除了其他问题之外，该方法可以容易地自动化进行批量生产。

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