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    • 71. 发明授权
      US5842111A Customer premise equipment for use with a fiber access architecture in a telecommunications network 失效
    • Customer premise equipment for use with a fiber access architecture in a telecommunications network
    • 用于在电信网络中与光纤接入架构一起使用的客户端设备
    • US5842111A
    • 1998-11-24
    • US701923
    • 1996-08-23
    • Charles Calvin Byers
    • Charles Calvin Byers
    • H04N21/643 , H04N7/173
    • H04N21/64307 , H04N7/22
    • The customer premise equipment of the invention consists of an OC-1, OC-3C or OC-12C receiver and an OC-1, OC-3C or OC-12C transmitter that interface with an ATM segmentation/reassembly circuit. In the downstream direction the segmentation/reassembly circuit receives the signals from the receiver and separates the signals into ATM cells. In the upstream direction the segmentation/reassembly circuit reassembles the ATM cells from the customer premise into a broadband signal and delivers the signal to the transmitter. The segmentation/reassembly circuit interfaces with a passive bus to deliver to and receive cells from a video decoder, POTS line card and a personal computer interface such that the customer can receive voice, data and video on a fiber to the home access architecture. A video system provides an ensemble of video channels at the customer premise.
    • 本发明的客户端设备由OC-1，OC-3C或OC-12C接收机和与ATM分段/重组电路接口的OC-1，OC-3C或OC-12C发射机组成。 在下游方向，分段/重组电路接收来自接收机的信号，并将信号分离成ATM信元。 在上游方向，分段/重组电路将ATM信元从客户端重新组合成宽带信号，并将信号传送到发射机。 分段/重新组合电路与无源总线相连接，以从视频解码器，POTS线卡和个人计算机接口传送和接收单元，使得客户可以将光纤上的语音，数据和视频接收到家庭接入架构。 视频系统在客户端提供视频通道的集合。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 72. 发明授权
      US5828414A Reduction of timing jitter in audio-video transport streams 失效
    • Reduction of timing jitter in audio-video transport streams
    • 降低音视频传输流中的定时抖动
    • US5828414A
    • 1998-10-27
    • US606197
    • 1996-02-23
    • Michael G. Perkins , Thomas Lookabaugh
    • Michael G. Perkins , Thomas Lookabaugh
    • H04N21/43 , H04N21/434 , H04N21/643 , H04N7/12
    • H04N21/4305 , H04N21/4344 , H04N21/64307
    • A method and apparatus for reducing program clock reference (PCR) jitter in transport packets of a transport stream compliant with MPEG-2 or another suitable audio-video encoding standard. The PCRs from a given single program transport stream (SPTS) of a multi-program transport stream are processed in a phase-locked loop (PLL) to generate dejittered PCRs for that SPTS. The PLL for a given SPTS receives as inputs the PCRs from that SPTS and a cycle count for each PCR indicative of the number of asynchronous clock cycles counted since the previous PCR. The PLL generates a given dejittered PCR as a function of the previous dejittered PCR, the cycle count for the given PCR, and a clock frequency mismatch estimate for the given program clock. The clock frequency mismatch estimate is generated by filtering a sequence of jitter estimates, each corresponding to the difference between a previous PCR and its corresponding dejittered PCR. The SPTS transport packets may then be restamped with the dejittered PCRs from the PLL to provide a dejittered multi-program transport stream.
    • 一种用于减少符合MPEG-2或其他合适的音频 - 视频编码标准的传输流的传输分组中的节目时钟参考（PCR）抖动的方法和装置。 来自多节目传输流的给定单个节目传输流（SPTS）的PCR在锁相环（PLL）中被处理，以产生针对该SPTS的解聚PCR。 给定SPTS的PLL接收来自该SPTS的PCR作为输入，并且每个PCR的循环计数指示自先前PCR以来计数的异步时钟周期的数量。 PLL产生给定的去抖动PCR作为先前的去极化PCR的函数，给定PCR的循环计数以及给定程序时钟的时钟频率失配估计。 时钟频率失配估计是通过对抖动估计序列进行滤波而产生的，每个抖动估计对应于先前的PCR与其对应的去极化PCR之间的差异。 然后可以使用来自PLL的去抖动PCR来修复SPTS传输分组，以提供解复用的多节目传输流。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 73. 发明授权
      US5802119A Adaptive clock recovery apparatus for supporting multiple bit transmission rates 失效
    • Adaptive clock recovery apparatus for supporting multiple bit transmission rates
    • 用于支持多位传输速率的自适应时钟恢复装置
    • US5802119A
    • 1998-09-01
    • US754093
    • 1996-11-20
    • Dong Bum Jung , Hun Kang
    • Dong Bum Jung , Hun Kang
    • H04L7/00 , H04J3/06 , H04N21/43 , H04N21/44 , H04N21/643
    • H04N21/44004 , H04J3/0632 , H04N21/4305 , H04N21/64307
    • An adaptive clock recovery apparatus. The adaptive clock recovery apparatus comprises a clock switching unit for switching a sample clock to be input from outside according to an adaptive clock controlling signal; a sample counting unit for inputting both a reset signal from the outside and an output from the clock switching unit, and outputting sample data by an operation depending upon a buffer state signal; an adaptive clock controlling unit for inputting the sample clock, the buffer state signal, the reset signal, and the sample data from the sample counting unit, and outputting the adaptive clock controlling signal to the clock switching unit; a reception frequency processing unit for inputting reception frequency from outside, and outputting frequency set up data; an adaptive clock generating unit for inputting both the frequency set up data from the reception frequency processing unit and the adaptive clock controlling signal from the adaptive clock controlling unit, and outputting the adaptive clock to the outside; and a buffering unit for outputting image data input from outside to the outside according to the adaptive clock of the adaptive clock generating unit, and also outputting the buffer state signal to the adaptive clock controlling unit and the sample counting unit, respectively.
    • 一种自适应时钟恢复装置。 自适应时钟恢复装置包括：时钟切换单元，用于根据自适应时钟控制信号切换从外部输入的采样时钟; 用于输入来自外部的复位信号和来自时钟切换单元的输出的采样计数单元，并且根据缓冲器状态信号通过操作输出采样数据; 自适应时钟控制单元，用于从采样计数单元输入采样时钟，缓冲器状态信号，复位信号和采样数据，并将自适应时钟控制信号输出到时钟切换单元; 接收频率处理单元，用于从外部输入接收频率，并输出频率设置数据; 自适应时钟发生单元，用于从接收频率处理单元输入频率设置数据和来自自适应时钟控制单元的自适应时钟控制信号，并将自适应时钟输出到外部; 以及缓冲单元，用于根据自适应时钟生成单元的自适应时钟输出从外部向外部输入的图像数据，并且还将缓冲器状态信号分别输出到自适应时钟控制单元和采样计数单元。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 77. 发明授权
      US5715285A Data transmission apparatus, a data receiving apparatus, and a data transmission system 失效
    • Data transmission apparatus, a data receiving apparatus, and a data transmission system
    • 数据发送装置，数据接收装置和数据传输系统
    • US5715285A
    • 1998-02-03
    • US573301
    • 1995-12-15
    • Kazuya Yamada
    • Kazuya Yamada
    • H04L7/033 , H04L12/70 , H04L12/951 , H04N7/62 , H04Q3/00 , H04Q11/04 , H03D3/24
    • H04N21/64307 , H04N21/242 , H04N21/4305 , H04Q11/0478 , H04L2012/5616 , H04L2012/5674
    • In a data transmission system having a transmission apparatus and a receiving apparatus through a network which supplies first and second network clock signals to the transmission and receiving apparatus respectively, synchronizing signal generation portions in both apparatus generate first and second periodical signals generated from the first and second network clock signals having a constant phase relation therebetween. The transmission apparatus generates time information indicating a data encoding timing according to a system clock signal of the transmission apparatus and supplies the time information in response to the first periodical signal and transmits the time information with data to be transmitted to the receiving apparatus. The receiving apparatus detects and holds the time information and uses it for controlling a PLL circuit for generating a system clock signal of the receiving apparatus such that the system clock signal of the transmission apparatus is substantially in phase with that of the receiving apparatus. When an error in the PLL circuit is larger than a controllable range, the time information is loaded into a counter in the PLL circuit. Thus, the PLL circuit operates correctly when there is a jitter of the transmitting data which occurs on packetting data in the ATM network.
    • 在具有通过网络的发送装置和接收装置的数据传输系统中，分别向发送和接收装置提供第一和第二网络时钟信号，两个装置中的同步信号产生部分产生从第一和第二周期信号产生的第一和第二周期信号， 第二网络时钟信号之间具有恒定的相位关系。 发送装置根据发送装置的系统时钟信号，生成表示数据编码定时的时间信息，并根据第一周期信号提供时刻信息，并将时间信息发送到接收装置发送的数据。 接收装置检测并保持时间信息，并使用它来控制用于产生接收装置的系统时钟信号的PLL电路，使得发送装置的系统时钟信号与接收装置的系统时钟信号基本相同。 当PLL电路中的错误大于可控范围时，时间信息被加载到PLL电路的计数器中。 因此，当在ATM网络中的分组数据上出现发送数据的抖动时，PLL电路正常工作。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 78. 发明授权
      US5699359A Audio-video and control interfaces for multi-media personal computer packet communication 失效
    • Audio-video and control interfaces for multi-media personal computer packet communication
    • 用于多媒体个人计算机分组通信的音视频和控制接口
    • US5699359A
    • 1997-12-16
    • US456625
    • 1995-06-01
    • Takaaki Suga
    • Takaaki Suga
    • H04N7/14 , H04L12/64 , H04L12/70 , H04L12/951 , H04N21/643 , H04Q3/00 , H04J3/24
    • H04L12/5601 , H04L12/6402 , H04L49/1553 , H04L49/30 , H04L49/3009 , H04N21/4108 , H04N21/4143 , H04N21/43615 , H04N21/4363 , H04N21/44231 , H04N21/64307 , H04N7/52 , H04L2012/5615 , H04L2012/5616 , H04L2012/5652 , H04L2012/5664 , H04L2012/5671
    • A multimedia communications apparatus allows a multimedia personal computer to freely select a unit with which to communicate, so that the circuit usage efficiency of a network connected to the multimedia communications apparatus will be increased. The multimedia communications apparatus has a packet generator/separator, a packet type detector, a controller, and a table. The table stores data representing the correspondence between addresses of interfaces of the multimedia personal computer and AV devices and addresses thereof on the network. For communications, the controller refers to the table to establish logic paths from a unit with which to communicate and a transmission range depending on multimedia such as moving-image data, sound data, or the like to be transmitted, and rewrites the headers of packets based on the established logic paths. The packet type detector captures empty packets required for each session of communications, and the packet generator/separator updates a destination unit address, inserts multimedia information, and transmits the packets to the destination unit address. Upon completion of the transmission, the packet generator/separator releases the packets from the dedicated state.
    • 多媒体通信装置允许多媒体个人计算机自由地选择要与之通信的单元，从而增加连接到多媒体通信装置的网络的电路使用效率。 多媒体通信装置具有包发生器/分离器，包类型检测器，控制器和表。 该表存储表示多媒体个人计算机和AV设备的接口的地址与网络上的地址之间的对应关系的数据。 对于通信，控制器参考该表来建立来自要进行通信的单元的逻辑路径和取决于要发送的诸如运动图像数据，声音数据等的多媒体的传输范围，并且重写分组的报头 基于既定的逻辑路径。 分组类型检测器捕获每个通信会话所需的空分组，并且分组生成器/分离器更新目的地单元地址，插入多媒体信息，并将分组发送到目的地单元地址。 在传输完成时，分组生成器/分离器从专用状态释放分组。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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