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71. 发明申请

US20090232033A1 Hybrid frequency compensation network 失效
标题翻译：混合频率补偿网络
公开(公告)号：US20090232033A1
公开(公告)日：2009-09-17
申请号：US12284773
申请日：2008-09-24
申请人： Patrick Isakanian , Kenneth C. Dyer
发明人： Patrick Isakanian , Kenneth C. Dyer
IPC分类号： H04B1/56
CPC分类号： H04L47/6245 , G06F1/10 , H03L7/00 , H04B3/32 , H04J3/0697 , H04L25/0278 , H04L43/16 , H04L47/25 , H04L47/521 , H04L47/6215 , H04L47/722
摘要： Hybrid frequency compensation is provided. Hybrid circuits are used to subtract the transmit signal from the receive signal in a full duplex communication system. Since the hybrid circuit and the main line driver are exposed to different loads, accurate subtraction is difficult to achieve. A frequency dependent network is used to match the loading seen by the driver and the hybrid. The compensation network can be based on active and/or passive components.
摘要翻译：提供混合频率补偿。混合电路用于在全双工通信系统中从接收信号中减去发送信号。由于混合电路和主线驱动器暴露于不同的负载，因此难以实现精确的减法。使用频率相关网络来匹配驾驶员和混合动力车辆所看到的负载。补偿网络可以基于主动和/或无源组件。

72. 发明申请

US20090225648A1 10GBASE-T training algorithm 审中-公开
标题翻译： 10GBASE-T训练算法
公开(公告)号：US20090225648A1
公开(公告)日：2009-09-10
申请号：US12284959
申请日：2008-09-26
申请人： Praveen Gopalapuram , Manl Kumaran , Tamleigh Rose
发明人： Praveen Gopalapuram , Manl Kumaran , Tamleigh Rose
IPC分类号： H04L12/24
CPC分类号： H04L47/6245 , G06F1/10 , H03L7/00 , H04B3/32 , H04J3/0697 , H04L25/0278 , H04L43/16 , H04L47/25 , H04L47/521 , H04L47/6215 , H04L47/722
摘要： A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10 GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.
摘要翻译：提供了一种识别和校正以太网10 GBase-T布线中发射机和接收机之间的线对可能发生的每个变化的方法。该方法包括四对线对A，B，C和D，一个极性交换和扰频器状态机，用于确定所选择的对是否匹配对A的要求。从接头状态机生成正确的B，C和D模式的规则基于选择为对A的对。电缆B，C和D被迭代地交换以将对映射重新排列成极性交换状态机，并且偏移状态机识别不同对之间的等待时间差。如果规则不满足，则在交换状态机处指定新的对A，并重复该过程，直到规则被满足为止。

73. 发明申请

US20040131066A1 Electronic switching circuit and method for a communication interface with cut through buffer memory 审中-公开
标题翻译：电子切换电路和通信接口的切割缓冲存储器的方法
公开(公告)号：US20040131066A1
公开(公告)日：2004-07-08
申请号：US10471666
申请日：2003-09-18
发明人： Franz-Josef Gotz
IPC分类号： H04L012/56
CPC分类号： H04L47/6245 , H04L47/50
摘要： The invention relates to an electronic switching circuit for a scalable communications interface between a first communication connection (16) having a first transmission cycle (17) with a first length and a second communication connection (12) having a second transmission cycle (13) with a second length, and comprising a receiving list (5, 15, 19, 33) for the first transmission cycle and a sending list (6, 14, 18, 31) for the second transmission cycle, wherein an element of the sending list is assigned to a data message (20, 21, 22, 23, 24, 25, 26, 27, 28) received in accordance with the receiving list, and having a cut-through buffer memory (8, 35) for a data message received in accordance with the receiving list and a data message to be sent in accordance with the sending list.
摘要翻译：本发明涉及一种用于在具有第一长度的第一传输周期（17）和具有第二传输周期（13）的第二通信连接（12）的第一通信连接（16）之间的可伸缩通信接口的电子切换电路，第二长度，并且包括用于第一传输周期的接收列表（5,15,19,33）和用于第二传输周期的发送列表（6,14,18,31），其中发送列表的元素是分配给根据接收列表接收的数据消息（20,21,22,23,24,25,26,27,28），并且具有用于接收的数据消息的直通缓冲存储器（8,35）根据接收列表和根据发送列表发送的数据消息。

74. 发明申请

US20020089927A1 System and method for synchronizing data trasnmission across a variable delay interface 审中-公开
标题翻译：跨可变延迟接口同步数据传输的系统和方法
公开(公告)号：US20020089927A1
公开(公告)日：2002-07-11
申请号：US09849053
申请日：2001-05-04
发明人： Michael A. Fischer , David J. Leach, JR. , Jack B. Hughes
IPC分类号： H04J003/14
CPC分类号： H04L1/16 , H04L1/08 , H04L1/1877 , H04L47/10 , H04L47/13 , H04L47/14 , H04L47/2433 , H04L47/31 , H04L47/32 , H04L47/50 , H04L47/564 , H04L47/6245 , H04W28/14 , H04W56/00 , H04W72/12 , H04W80/00
摘要： A method of synchronizing data transmission between a host computer system and a transmitter across an interface with variable delay or latency. The host computer system marks transition frames between successive transmission intervals and transfers the outgoing frames across the variable interface to the transmitter. The transmitter enqueues outgoing frames into one or more FIFO transmission queue(s) and processes the enqueued frames as appropriate for the communication protocol in use. Marked frames are detected as they reach the head of the appropriate transmit queue. In particular, while bypassing is not active, the transmitter transmits unmarked frames until the end of the current interval, or until there is insufficient time in the interval to transmit another frame or until a marked frame is detected. While bypassing is not active, the transmitter terminates transmission from the transmit queue when a marked frame is detected during each interval. While bypassing is active, the transmitter discards unmarked frames without transmission until a marked frame is detected. During each interval, the transmitter activates bypassing if a marked frame has not been detected and deactivates bypassing if a marked frame is detected while bypassing is active. The transmitter enables queue mark operation if a marked frame is detected while queue mark operation is not enabled. The transmitter increments a bypass counter each time an interval ends without detecting a marked frame, and disables queue mark operation if the bypass counter reaches a predefined limit.
摘要翻译：一种在主计算机系统和发射机之间通过具有可变延迟或延迟的接口同步数据传输的方法。主计算机系统标记连续传输间隔之间的过渡帧，并将可移动接口的输出帧传送到发射机。发射机将输出帧排队到一个或多个FIFO传输队列中，并根据正在使用的通信协议处理入队帧。当它们到达适当传输队列的头部时，检测到标记帧。特别地，当旁路不活动时，发射机发送未标记的帧直到当前时间间隔结束，或者直到间隔内的时间不足以发送另一个帧或直到检测到标记的帧。当旁路不活动时，当在每个间隔期间检测到标记的帧时，发射机终止来自发射队列的传输。当旁路有效时，发射机将丢弃未标记的帧，直到检测到标记的帧。在每个间隔期间，如果未检测到标记的帧，发射器将激活旁路，如果在旁路有效时检测到标记的帧，则会禁用旁路。如果未启用队列标记操作，则检测到标记的帧时，发送器启用队列标记操作。发射机每次间隔结束时都会增加旁路计数器，而不检测到标记的帧，如果旁路计数器达到预定义的限制，则禁用队列标记操作。

75. 发明授权

US06327625B1 FIFO-based network interface supporting out-of-order processing 有权
标题翻译：基于FIFO的网络接口支持无序处理
公开(公告)号：US06327625B1
公开(公告)日：2001-12-04
申请号：US09451395
申请日：1999-11-30
申请人： Chi-Lie Wang , Li-Jau Yang , Ngo Thanh Ho
发明人： Chi-Lie Wang , Li-Jau Yang , Ngo Thanh Ho
IPC分类号： G06F1516
CPC分类号： H04L63/0236 , H04L47/2441 , H04L47/34 , H04L47/50 , H04L47/624 , H04L47/6245
摘要： Support for priority and IP security packets, and other protocols at the network interface level and in conjunction with FIFO-based packet buffers is provided by allowing out of order processing of certain packets in the FIFO. The optimized character of FIFO for sequential transfer is maintained, while particular types of packets are processed out of order to achieve minimum latency and maximum data security in an intelligent network interface card. A buffer stores data packets in an order of receipt. Logic is included in the network interface to transfer packets out of the buffer according to the order of receipt, and according to the respective packet types so that packets having a particular packet type are transferred out of the order of receipt relative to packets having other packet types.
摘要翻译：通过允许对FIFO中的某些数据包进行故障处理，来支持优先级和IP安全性数据包以及网络接口级别的其他协议以及基于FIFO的数据包缓冲区。维持用于顺序传输的FIFO的优化特性，同时特定类型的数据包处理不正常，以实现智能网络接口卡中的最小延迟和最大数据安全性。缓冲器以接收顺序存储数据包。逻辑包括在网络接口中，以根据接收顺序将数据包从缓冲器传送出去，并根据各自的分组类型，使得具有特定分组类型的分组相对于具有其他分组的分组被传送出接收顺序类型。

76. 发明申请

US20180212894A1 FORK TRANSFER OF DATA BETWEEN MULTIPLE AGENTS WITHIN A RECONFIGURABLE FABRIC 审中-公开
公开(公告)号：US20180212894A1
公开(公告)日：2018-07-26
申请号：US15924873
申请日：2018-03-19
申请人： Wave Computing, Inc.
发明人： Christopher John Nicol , Sam Brandon Sandbote
IPC分类号： H04L12/863 , H04L12/861
CPC分类号： H04L47/6245 , G06F13/1673 , G06F13/1689 , G06F13/1694 , H04L47/6225 , H04L49/90
摘要： Techniques are disclosed for managing data within a reconfigurable computing environment. In a multiple processing element environment, such as a mesh network, or other suitable topology, there is a need to pass data between processing elements. In many instances when multiple processing elements are working together to perform a given task, it is desirable to improve parallelism where possible to decrease overall execution time. An upstream processing element performs a fork operation to provide data to multiple downstream processing elements. The processing elements within the reconfigurable fabric are controlled by circular buffers. The circular buffers are statically scheduled. The fork operation provides for computation to be divided amongst multiple processing elements. An efficient forking mechanism is a key component in achieving optimal performance of a multiple processing element system.

77. 发明申请

US20180176144A1 APPARATUS FOR SELF-REGULATER (SR) LAST-IN, FIRST-OUT (LIFO) SCHEDULING IN SOFTWARE DEFINED NETWORKS (SNDs) WITH HYBRID TRAFFIC 审中-公开
公开(公告)号：US20180176144A1
公开(公告)日：2018-06-21
申请号：US15383905
申请日：2016-12-19
申请人： Futurewei Technologies, Inc.
发明人： Min Luo , Shih-Chun Lin , Ian F. Akyildiz
IPC分类号： H04L12/863 , H04L12/933 , H04L12/875
CPC分类号： H04L47/6245 , H04L47/56
摘要： An apparatus, such as a network element, comprises a receiver to receive a plurality of packets from a plurality of traffic flows and a first non-transitory memory to form a first and second set of queues to store the plurality of packets from the plurality of traffic flows. One or more processors execute instructions stored in a second non-transitory memory to limit a rate of transfer of the plurality of packets that is output from the first set of queues to the second set of queues having a plurality of delays. A packet stored in the second set of queues is selected to be output based on a comparison of the plurality of delays.

78. 发明授权

US09935890B2 Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method 有权
公开(公告)号：US09935890B2
公开(公告)日：2018-04-03
申请号：US15092696
申请日：2016-04-07
申请人： Panasonic Corporation
发明人： Peter Klenner
IPC分类号： H04L12/863 , H03M13/27 , H04L1/00
CPC分类号： H04L47/6245 , H03M13/27 , H03M13/271 , H03M13/2732 , H03M13/276 , H03M13/2785 , H03M13/2796 , H04L1/0071 , H04L1/0076 , H04L1/0085 , H04L47/6255
摘要： A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a first connection destination of an input terminal of the convolutional interleaver to one end of one of a plurality of branches; a plurality of FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a second connection destination of an output terminal of the convolutional interleaver to the other end of one of the plurality of branches. The first and second switches switch the first and second connection destinations, respectively, when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the first and second connection destinations sequentially and repeatedly among the plurality of branches.

79. 发明申请

US20180034649A1 NODE UNIT INCLUDING QUEUING ENGINE FOR MULTICASTING ETHERNET DATA AND DISTRIBUTED ANTENNA SYSTEM INCLUDING THE SAME 审中-公开
公开(公告)号：US20180034649A1
公开(公告)日：2018-02-01
申请号：US15540638
申请日：2015-12-30
申请人： SOLiD, INC.
发明人： Doyoon KIM
IPC分类号： H04L12/18 , H04L12/861
CPC分类号： H04L12/18 , H04L12/189 , H04L45/66 , H04L47/32 , H04L47/6245 , H04L49/90
摘要： Provided are a node unit including a queuing engine for multicasting Ethernet data, and a distributed antenna system including the same. The node unit is a node unit which is branch-connected to a plurality of lower nodes, and comprises: a media access control (MAC) module; and a queuing engine for interfacing Ethernet data between the MAC module and the plurality of branch-connected lower nodes, wherein the queuing engine multicasts Ethernet data received from the MAC module to the plurality of branch-connected lower nodes, transfers Ethernet data received from the plurality of branch-connected lower nodes to the MAC module, wherein the queuing engine comprises a buffer for buffering Ethernet data received from the plurality of branch-connected lower nodes, and outputting the buffered Ethernet data to the MAC module.

80. 发明授权

US09848446B2 System and methods for synchronizing edge devices on channels without carrier sense 有权
公开(公告)号：US09848446B2
公开(公告)日：2017-12-19
申请号：US15184642
申请日：2016-06-16
申请人： Astrolink International LLC , Dominion Energy Technologies, Inc.
发明人： Marcia R. Martin , Andrew Louis Abendschein , Henrick F. Bernheim
IPC分类号： H04W74/08 , H04W56/00 , H04L7/04 , H04L12/24 , H04L12/863 , H04W28/06
CPC分类号： H04W74/0891 , H04L7/04 , H04L41/5022 , H04L47/6245 , H04W28/065 , H04W56/00
摘要： A system and method are disclosed for synchronizing edge devices on a network, wherein the network has limited bandwidth and does not support a practical carrier sense mechanism. The edge devices transmit, using a slotted protocol, to a server located at a central data aggregation point. The server also controls a Central Transmitter, which sends messages to the edge devices to assign transmission slots and provide timing information to the edge devices to ensure that transmissions sent by devices sharing the same communication channel do not collide.

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