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71. 发明授权

US07433253B2 Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module 有权
标题翻译：集成电路，集成电路的操作方法，集成电路的制造方法，存储器模块，可堆叠存储器模块
公开(公告)号：US07433253B2
公开(公告)日：2008-10-07
申请号：US11768508
申请日：2007-06-26
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02 , G11C11/00
CPC分类号： G11C7/067 , G11C5/02 , G11C5/04 , G11C11/1673 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/71 , G11C2213/79
摘要： An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.
摘要翻译：集成电路具有电流检测放大器，其包括具有第一输入，第二输入和输出的电压比较器; 耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置，耦合在电压比较器的第二输入端和第二输入信号节点之间的第二钳位装置，具有第一侧和第二电流镜第一侧包括耦合在电压源和第一钳位装置之间的第一晶体管和电流镜第二侧，其包括耦合在电压源和第二钳位装置之间的第二晶体管，以及感测方案，包括主动平衡耦合到第二晶体管的源极和漏极的电容。

72. 发明申请

US20080205158A1 READING METHOD AND CIRCUIT FOR A NON-VOLATILE MEMORY DEVICE BASED ON THE ADAPTIVE GENERATION OF A REFERENCE ELECTRICAL QUANTITY 有权
标题翻译：基于参考电量自适应生成的非易失性存储器件的读取方法和电路
公开(公告)号：US20080205158A1
公开(公告)日：2008-08-28
申请号：US12031645
申请日：2008-02-14
申请人： Giovanni Pagano , Pierluca Guarino , Edoardo Nocita
发明人： Giovanni Pagano , Pierluca Guarino , Edoardo Nocita
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/067 , G11C7/062 , G11C16/349 , G11C2207/063
摘要： A circuit for determining the value of a datum stored in an array memory cell of a non-volatile memory device having at least one reference memory cell of known content. The circuit has a determination stage, which compares an array electrical quantity, correlated to a current flowing in the array memory cell, with a reference electrical quantity, and supplies an output signal indicative of the datum, based on the comparison; and a generator circuit, provided with an input receiving a target electrical quantity correlated to a current flowing in use in the reference memory cell, and an output, which supplies the reference electrical quantity with a controlled value close or equal to that of the target electrical quantity. The generator circuit is provided with a variable generator, and a control unit connected to, and designed to control, the variable generator so that it will generate the controlled value of the reference electrical quantity.
摘要翻译：一种用于确定存储在具有已知内容的至少一个参考存储器单元的非易失性存储器件的阵列存储器单元中的数据的值的电路。电路具有判定级，其将与阵列存储单元中流动的电流相关联的阵列电量与参考电量进行比较，并且基于该比较来提供表示基准的输出信号; 以及发生器电路，其具有接收与在基准存储单元中使用的电流相关的目标电量的输入端和输出端，所述输出以与所述目标电气接近或相等的受控值提供所述参考电量数量。发电机电路设置有可变发电机，以及连接到并被设计成控制可变发电机从而产生参考电量的受控值的控制单元。

73. 发明授权

US07388409B2 Offset independent sense circuit and method 失效
标题翻译：偏移独立检测电路和方法
公开(公告)号：US07388409B2
公开(公告)日：2008-06-17
申请号：US11882639
申请日：2007-08-03
申请人： Chung-Lung Pai
发明人： Chung-Lung Pai
IPC分类号： G01R19/00
CPC分类号： G11C7/067 , G11C7/062 , G11C2207/063
摘要： An offset current independent sense circuit is switchable between a store state and a sense state. In the store state, the sense circuit stores an offset current to a capacitor, and the influence of the offset current is eliminated by a transistor to regenerate the offset current based on a signal provided by the capacitor in the sense state.
摘要翻译：偏移电流独立检测电路可在存储状态和感测状态之间切换。在存储状态下，感测电路将偏移电流存储到电容器，并且通过晶体管消除偏移电流的影响，以在感测状态下基于由电容器提供的信号再生偏移电流。

74. 发明申请

US20080137430A1 LOW-VOLTAGE READING DEVICE IN PARTICULAR FOR MRAM MEMORY 有权
标题翻译：低电压读取器件，特别适用于MRAM存储器
公开(公告)号：US20080137430A1
公开(公告)日：2008-06-12
申请号：US12033795
申请日：2008-02-19
申请人： Jean Lasseuguette
发明人： Jean Lasseuguette
IPC分类号： G11C16/04
CPC分类号： G11C11/16 , G11C7/062 , G11C7/14 , G11C2207/063
摘要： The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.
摘要翻译：本发明涉及一种用于读取位线的单元的电路，包括分别用于控制位线的第一和第二晶体管和与参考线相连的参考晶体管，连接到第二控制晶体管的参考晶体管和连接到基准电流的写入晶体管到第一控制晶体管，用于比较位线的电流和参考电流，其特征在于，第一中间晶体管连接到并行于第一控制晶体管的写入晶体管，并且第二中间晶体管连接在第栅极和漏极与第二控制晶体管并联，并且偏振晶体管分别串联连接到中间晶体管，以便在参考电流上叠加电流。

75. 发明申请

US20080094919A1 Noise resistant small signal sensing circuit for a memory device 有权
公开(公告)号：US20080094919A1
公开(公告)日：2008-04-24
申请号：US12002057
申请日：2007-12-14
申请人： R. Baker
发明人： R. Baker
IPC分类号： G11C7/02 , G11C7/06
CPC分类号： G11C7/02 , G11C7/06 , G11C7/062 , G11C7/067 , G11C11/16 , G11C13/004 , G11C2207/063 , G11C2207/068
摘要： Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

76. 发明授权

US07324382B2 Current-mode sensing structure used in high-density multiple-port register in logic processing and method for the same 失效
标题翻译：电流模式感测结构用于高密度多端口寄存器的逻辑处理和方法相同
公开(公告)号：US07324382B2
公开(公告)日：2008-01-29
申请号：US11443037
申请日：2006-05-31
申请人： Jew-Yong Kuo
发明人： Jew-Yong Kuo
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C7/062 , G11C7/067 , G11C7/14 , G11C2207/063
摘要： A current-mode sensing structure used in a high-density multiple-port register in logic processing and a method for the same are proposed. First, a reference current is defined by a dummy word line of a dummy cell and output. A multiple-port register file cell is then used to send out a select signal of “0” or “1” and output a cell current according to the select signal and the reference current. Finally, the cell current and the reference current are sent to a current comparator amplifier, which senses and outputs a difference value between the cell current and the reference current to perform session at once (SAO) recording. Because the difference value has only two possibilities: the reference current or its negative, the sensing time of the current comparator amplifier can be shortened.
摘要翻译：提出了在逻辑处理中的高密度多端口寄存器中使用的电流模式感测结构及其方法。首先，参考电流由虚拟单元的虚拟字线定义并输出。然后使用多端口寄存器文件单元发出选择信号“0”或“1”，并根据选择信号和参考电流输出单元电流。最后，将电池电流和参考电流发送到电流比较器放大器，其感测并输出电池电流和参考电流之间的差值，以一次（SAO）记录执行会话。由于差分值只有两种可能：参考电流或负值，可以缩短电流比较放大器的检测时间。

77. 发明授权

US07319627B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07319627B2
公开(公告)日：2008-01-15
申请号：US11448521
申请日：2006-06-07
申请人： Kazuo Taguchi
发明人： Kazuo Taguchi
IPC分类号： G11C7/02
CPC分类号： G11C16/26 , G11C7/067 , G11C2207/063 , G11C2216/10
摘要： A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit including a first mirror transistor and a second mirror transistor of a mirror circuit. A selection gate transistor and a detection transistor of the selected non-volatile memory cell are included as part of a load circuit connected to a drain electrode of the second mirror transistor. The detection transistor has a drain electrode linked to a source electrode of the selection gate transistor. An operating current of the selection gate transistor is smaller than an operating current of the detection transistor, and an electric current output from the second mirror transistor is determined by the operating current of the selection gate transistor. This arrangement enables determination of the stable operating current of the memory cell irrespective of the state of a floating gate of the detection transistor. Data corresponding to the writing condition of the memory cell is thus stably output from the sense amplifier circuit, based on the stable operating current of the memory cell.
摘要翻译：用于非易失性半导体存储器件的读出放大器电路用于输出写入所选择的非易失性存储单元中的数据，并被构造为包括镜电路的第一镜像晶体管和第二反射镜晶体管的电流镜电路。所选择的非易失性存储单元的选择栅晶体管和检测晶体管被包括在连接到第二反射镜晶体管的漏极的负载电路的一部分上。检测晶体管具有连接到选择栅极晶体管的源电极的漏电极。选择栅极晶体管的工作电流小于检测晶体管的工作电流，并且从第二反射镜晶体管输出的电流由选择栅晶体管的工作电流决定。这种布置使得能够确定存储器单元的稳定工作电流，而与检测晶体管的浮置栅极的状态无关。因此，基于存储单元的稳定工作电流，从读出放大器电路稳定地输出与存储单元的写入条件对应的数据。

78. 发明授权

US07312641B2 Sense amplifiers with high voltage swing 有权
标题翻译：具有高电压摆幅的感应放大器
公开(公告)号：US07312641B2
公开(公告)日：2007-12-25
申请号：US11024257
申请日：2004-12-28
申请人： Takao Akaogi , Sameer Wadhwa , Michael Achter , Bhimachar Venkatesh
发明人： Takao Akaogi , Sameer Wadhwa , Michael Achter , Bhimachar Venkatesh
IPC分类号： G01R19/00 , G11C7/00
CPC分类号： G11C7/062 , G11C2207/063 , H03F3/345 , H03F3/45183 , H03F3/45475 , H03F2200/462 , H03F2200/78
摘要： A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.
摘要翻译：读出放大器包括用于产生参考输出电压的参考电压发生器和用于产生核心输出电压的核心输出电压发生器。核心输出电压发生器包括核心前端级和核心后端级，或者包括多个放大器晶体管，每个放大器晶体管通过诸如核心单元之类的电流传导器件导通核心电流的一部分。这种组件的晶体管的尺寸和/或连接导致高电压摆动，从而导致读出放大器的高灵敏度。

79. 发明申请

US20070280021A1 SENSE AMPLIFIER 有权
标题翻译：感应放大器
公开(公告)号：US20070280021A1
公开(公告)日：2007-12-06
申请号：US11749412
申请日：2007-05-16
申请人： Yoshihiro Ueda , Yoshihisa Iwata , Toshiaki Edahiro , Toshihiro Suzuki
发明人： Yoshihiro Ueda , Yoshihisa Iwata , Toshiaki Edahiro , Toshihiro Suzuki
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C7/065 , G11C7/062 , G11C7/12 , G11C11/1673 , G11C16/0491 , G11C16/26 , G11C17/126 , G11C2207/002 , G11C2207/063
摘要： A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.
摘要翻译：根据本发明的示例的读出放大器具有触发器连接的第一，第二，第三和第四FET。第五FET的漏极连接到第一输入节点，并且其源极连接到电源节点。第六FET的漏极连接到第二输入节点，其源极连接到电源节点。通过用第一电流从第一输入节点充电第一输出节点并且通过用第二电流从第二输入节点充电第二输出节点来开始感测操作。开始感测操作后，第五和第六FET导通。

80. 发明申请

US20070280020A1 Semiconductor memory device having local sense amplifier 有权
标题翻译：具有局部读出放大器的半导体存储器件
公开(公告)号：US20070280020A1
公开(公告)日：2007-12-06
申请号：US11605974
申请日：2006-11-30
申请人： Chan-Yong Lee , Chi-Wook Kim
发明人： Chan-Yong Lee , Chi-Wook Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C2207/063
摘要： A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.
摘要翻译：半导体存储器件包括连接在位线读出放大器和电流检测型输入/输出（IO）读出放大器之间的本地读出放大器。位线读出放大器连接在位线对之间，位线对连接到本地数据IO对，并且本地数据IO对通过一对开关电路连接到全局数据IO对。在半导体存储器件的读取操作期间，本地数据IO对保持连接到全局数据IO对。

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