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    • 3. 发明申请
    • Semiconductor integrated circuit device and semiconductor memory using the same
    • 半导体集成电路器件和使用其的半导体存储器
    • US20050082613A1
    • 2005-04-21
    • US10917500
    • 2004-08-13
    • Kazuo Taguchi
    • Kazuo Taguchi
    • H01L21/28H01L21/8238H01L21/8244H01L21/84H01L27/092H01L27/11H01L27/12H01L29/423H01L29/49H01L29/786
    • H01L29/78615H01L21/84H01L27/1104H01L27/1203H01L29/42384H01L29/78621
    • Aspects of the invention can provide a semiconductor device including a transistor having a gate shape, which enables a source area and a body contact area to be connected without using wiring and with no gate part protruding to the source area side, and a semiconductor memory. The semiconductor device can have field regions, a transistor which includes a gate (L type gate), a gate insulating film directly below the gate, a body area directly below the gate insulating film, and a source area and a drain area formed on both sides which hold the body area in between. The gate can consist essentially of a first part extending along a channel width direction on the field region and a second part protruding from one end of the first part in the channel width direction to the drain side, and being formed in the L type gate in a plan view. A body contact area can be provided on the field region on the opposite side to the first part with the second part of the L type gate in between, and a low resistant layer is formed on a surface between the source area and the body contact area.
    • 本发明的方面可以提供一种半导体器件,其包括具有栅极形状的晶体管,其能够在不使用布线并且没有栅极部分突出到源极区侧的情况下连接源极区域和本体接触区域,以及半导体存储器。 半导体器件可以具有场区域,晶体管包括栅极(L型栅极),栅极正下方的栅极绝缘膜,栅极绝缘膜正下方的体区,以及形成在两者上的源极区和漏极区 身体区域之间的两侧。 栅极基本上可以由场区域上的沟道宽度方向延伸的第一部分和从沟道宽度方向上的第一部分的一端突出到漏极侧的第二部分形成在L型栅极中 一个平面图。 可以在与第一部分相反的一侧的场区域上设置体接触区域,其中L型栅极的第二部分在其间,并且在源区域和身体接触区域之间的表面上形成低阻力层 。
    • 6. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US08040728B2
    • 2011-10-18
    • US12469181
    • 2009-05-20
    • Kazuo Taguchi
    • Kazuo Taguchi
    • G11C16/04G11C11/34
    • G11C16/0433H01L27/11519H01L27/11521H01L27/11558H01L29/42324H01L29/42328H01L29/7883
    • A semiconductor integrated circuit includes a non-volatile memory built into the semiconductor integrated circuit, the non-volatile memory electrically writing and erasing data and including a memory cell, the memory cell including: a selecting transistor controlled by a word line; an impurity diffused region formed inside a semiconductor substrate, the impurity diffused region being coupled to one of a source and a drain of the selecting transistor; a first electrode formed above the semiconductor substrate with an insulating film therebetween, the first electrode receiving a control signal and part of the first electrode having an opening; a second electrode formed above the first electrode so as to oppose the first electrode with an insulating film therebetween, the second electrode having a protrusion which opposes the impurity diffused region with a tunnel film therebetween and projects toward the semiconductor substrate through the opening of the first electrode, and storing information based on an applied voltage; and a sensing transistor operating based on charges accumulated in the second electrode, so as to sense the information stored in the memory cell.
    • 半导体集成电路包括内置于半导体集成电路中的非易失性存储器,非易失性存储器电写入和擦除数据并包括存储单元,所述存储单元包括:由字线控制的选择晶体管; 形成在半导体衬底内部的杂质扩散区域,所述杂质扩散区域耦合到所述选择晶体管的源极和漏极之一; 形成在半导体衬底之上的第一电极,其间具有绝缘膜,所述第一电极接收控制信号,并且所述第一电极的一部分具有开口; 形成在所述第一电极上方以与所述第一电极相对的绝缘膜的第二电极,所述第二电极具有与所述杂质扩散区域相对的突起,所述突起与所述第一电极之间具有隧道膜,并且通过所述第一电极的开口朝向所述半导体基板突出 电极,并基于所施加的电压存储信息; 以及感测晶体管,其基于积累在所述第二电极中的电荷进行操作,以感测存储在所述存储单元中的信息。
    • 7. 发明授权
    • Semiconductor device and semiconductor memory using the same
    • 半导体器件和使用其的半导体存储器
    • US07279749B2
    • 2007-10-09
    • US10924995
    • 2004-08-25
    • Kazuo Taguchi
    • Kazuo Taguchi
    • H01L27/01H01L27/12H01L31/0392
    • G11C11/412H01L27/0207H01L27/1104H01L27/1203
    • Aspects of the invention can provide a semiconductor device and a semiconductor memory using the semiconductor device having a gate shape by which the width of the gate can be realized as designed even if relative shifts occur between the masks for forming the field regions and the gate patterns. The semiconductor device can include, in field regions, a gate (an H-type gate), a gate insulating film right under the gate, a body region right under the gate insulating film, and source/drain regions formed on both sides of and across the body region. The H-type gate can have a first section extending along the channel width direction on the field region, and a pair of second sections formed on both ends of the first section in the channel width direction and extending along the channel length direction, and is formed to be an H shape in plan view. Since a part of each of the pair of second sections of the H-type gate can be formed on a part of the field region having a constant length in the channel length direction, the channel width can be defined by the length of the first section.
    • 本发明的方面可以提供半导体器件和半导体存储器,其使用具有栅极形状的半导体器件,通过该栅极形状可以实现栅极的宽度,即使在用于形成场区域的掩模和栅极图案之间发生相对偏移 。 半导体器件可以在场区域中包括栅极(H型栅极),栅极正下方的栅极绝缘膜,栅极绝缘膜正下方的主体区域和形成在栅极绝缘膜两侧的源极/漏极区域 穿过身体区域。 H型栅极可以具有沿着场区域上的沟道宽度方向延伸的第一部分,以及在沟道宽度方向上形成在第一部分的两端并沿着沟道长度方向延伸的一对第二部分,并且是 在平面图中形成为H形。 由于H型栅极的一对第二部分中的每一个的一部分可以形成在沟道长度方向上具有恒定长度的场区域的一部分上,所以沟道宽度可以由第一部分的长度 。
    • 8. 发明申请
    • Memory device
    • 内存设备
    • US20060285407A1
    • 2006-12-21
    • US11448521
    • 2006-06-07
    • Kazuo Taguchi
    • Kazuo Taguchi
    • G11C7/02
    • G11C16/26G11C7/067G11C2207/063G11C2216/10
    • A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit including a first mirror transistor and a second mirror transistor of a mirror circuit. A selection gate transistor and a detection transistor of the selected non-volatile memory cell are included as part of a load circuit connected to a drain electrode of the second mirror transistor. The detection transistor has a drain electrode linked to a source electrode of the selection gate transistor. An operating current of the selection gate transistor is smaller than an operating current of the detection transistor, and an electric current output from the second mirror transistor is determined by the operating current of the selection gate transistor. This arrangement enables determination of the stable operating current of the memory cell irrespective of the state of a floating gate of the detection transistor. Data corresponding to the writing condition of the memory cell is thus stably output from the sense amplifier circuit, based on the stable operating current of the memory cell.
    • 用于非易失性半导体存储器件的读出放大器电路用于输出写入所选择的非易失性存储单元中的数据,并被构造为包括镜电路的第一镜像晶体管和第二反射镜晶体管的电流镜电路。 所选择的非易失性存储单元的选择栅晶体管和检测晶体管被包括在连接到第二反射镜晶体管的漏极的负载电路的一部分上。 检测晶体管具有连接到选择栅极晶体管的源电极的漏电极。 选择栅极晶体管的工作电流小于检测晶体管的工作电流,并且从第二反射镜晶体管输出的电流由选择栅晶体管的工作电流决定。 这种布置使得能够确定存储器单元的稳定工作电流,而与检测晶体管的浮置栅极的状态无关。 因此,基于存储单元的稳定工作电流,从读出放大器电路稳定地输出与存储单元的写入条件对应的数据。
    • 9. 发明授权
    • Semiconductor integrated circuit device and sense amplifier of memory
    • 半导体集成电路器件和存储器的读出放大器
    • US07098698B2
    • 2006-08-29
    • US10916611
    • 2004-08-12
    • Kazuo Taguchi
    • Kazuo Taguchi
    • H03F3/45
    • G11C7/062H01L27/1203
    • To provide a semiconductor integrated circuit device and a sense amplifier in a memory in which a transistor element whose body potential is variable is built in an appropriate location and which can produce high speed operation with a layout advantage, an SOI transistor integrated circuit, each source of p-channel MOS transistor Qp1 and Qp2 is given a high potential level Vdd, for example, a supply-power potential, and respective body potentials are set as variable potentials corresponding to mutually inverse signal inputs Vin and Bvin, and a control signal CS is given to each gate. Also, each source and body of n-channel MOS transistor Qn1 and Qn2 are given a low potential level Vsa, for example, an earth potential, the signal inputs Vin and Bvin are supplied to respective gates. A connection node of these drains of the transistors Qp1 and Qn1 is connected to a signal output section Vout. Also, a connection node of the drains of the transistors Qp2 and Qn2 is connected to a signal output section BVout.
    • 为了在存储器中提供半导体集成电路器件和读出放大器,其中体电位可变的晶体管元件内置在适当的位置并且可以以布局优势产生高速运算,SOI晶体管集成电路 给予p沟道MOS晶体管Qp 1和Qp 2高电位电平Vdd,例如电源电位,并且将各个体电位设置为对应于相互反向信号输入Vin和Bvin的可变电位,以及控制 信号CS被给予每个门。 此外,n沟道MOS晶体管Qn 1和Qn 2的每个源极和主体被赋予低电位Vsa,例如地电位,信号输入Vin和Bvin被提供给各个栅极。 晶体管Qp 1和Qn 1的这些漏极的连接节点连接到信号输出部分Vout。 此外,晶体管Qp 2和Qn 2的漏极的连接节点连接到信号输出部分BVout。
    • 10. 发明授权
    • Gas sensor with multiple mechanical and thermal shock cushion layers
    • 气体传感器具有多个机械和热冲击缓冲层
    • US06550309B1
    • 2003-04-22
    • US09219823
    • 1998-12-23
    • Keiichi NodaKazuo TaguchiHisaharu NishioKatsuhisa YabutaKoji KanoKoichi ShimamuraMitsuo Kusa
    • Keiichi NodaKazuo TaguchiHisaharu NishioKatsuhisa YabutaKoji KanoKoichi ShimamuraMitsuo Kusa
    • G02N2704
    • G01N27/407
    • A gas sensor 1 includes an outer cylinder 18, a metallic shell 3, and a sensor element 2. The metallic shell 3 is disposed inside the outer cylinder 18. The sensor element 2 is disposed in a through-hole 30 formed in the metallic shell 3 and is adapted to detect a component of a gas to be measured. A sealing material layer 32 is mainly made of glass and is disposed between the inner surface of the metallic shell 3 and the outer surface of the sensor element 2. A cushion layer 34 formed of a porous inorganic substance is disposed in contact with the end of the sealing material layer 32 on the front-end side with respect to the axial direction of the sensor element 2. A cushion layer 33 formed of talc glass is disposed in contact with the end of the sealing material layer 32 on the rear-end side with respect to the axial direction of the sensor element 2. A gas sensor according to the present invention is especially adapted for use in a motorcycle and includes a sensor element having lower susceptibility to mechanical shock or thermal stress induced by different rates of contraction between a sealing material layer and an adjacent component element as well as excellent durability.
    • 气体传感器1包括外筒18,金属壳3和传感器元件2.金属壳3设置在外筒18内。传感器元件2设置在形成在金属壳中的通孔30中 3,适于检测待测气体的成分。 密封材料层32主要由玻璃制成,并且设置在金属壳3的内表面和传感器元件2的外表面之间。由多孔无机物形成的缓冲层34设置成与 密封材料层32相对于传感器元件2的轴向在前端侧。由滑石玻璃形成的缓冲层33设置成与后端侧的密封材料层32的端部接触 相对于传感器元件2的轴向方向。根据本发明的气体传感器特别适用于摩托车,并且包括传感器元件,其对机械冲击的敏感性或由不同的收缩速率 密封材料层和相邻的组分元件以及优异的耐久性。