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1. 发明授权

US07525858B2 Semiconductor memory device having local sense amplifier 有权
标题翻译：具有局部读出放大器的半导体存储器件
公开(公告)号：US07525858B2
公开(公告)日：2009-04-28
申请号：US11605974
申请日：2006-11-30
申请人： Chan-Yong Lee , Chi-Wook Kim
发明人： Chan-Yong Lee , Chi-Wook Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C2207/063
摘要： A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.
摘要翻译：半导体存储器件包括连接在位线读出放大器和电流检测型输入/输出（IO）读出放大器之间的本地读出放大器。位线读出放大器连接在位线对之间，位线对连接到本地数据IO对，并且本地数据IO对通过一对开关电路连接到全局数据IO对。在半导体存储器件的读取操作期间，本地数据IO对保持连接到全局数据IO对。

2. 发明申请

US20070280020A1 Semiconductor memory device having local sense amplifier 有权
标题翻译：具有局部读出放大器的半导体存储器件
公开(公告)号：US20070280020A1
公开(公告)日：2007-12-06
申请号：US11605974
申请日：2006-11-30
申请人： Chan-Yong Lee , Chi-Wook Kim
发明人： Chan-Yong Lee , Chi-Wook Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/065 , G11C11/4091 , G11C2207/063
摘要： A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.
摘要翻译：半导体存储器件包括连接在位线读出放大器和电流检测型输入/输出（IO）读出放大器之间的本地读出放大器。位线读出放大器连接在位线对之间，位线对连接到本地数据IO对，并且本地数据IO对通过一对开关电路连接到全局数据IO对。在半导体存储器件的读取操作期间，本地数据IO对保持连接到全局数据IO对。

3. 发明申请

US20050036388A1 Method and apparatus for increasing data read speed in a semiconductor memory device 有权
标题翻译：用于增加半导体存储器件中的数据读取速度的方法和装置
公开(公告)号：US20050036388A1
公开(公告)日：2005-02-17
申请号：US10915036
申请日：2004-08-10
申请人： Chan-Yong Lee , Jung-Hwa Lee
发明人： Chan-Yong Lee , Jung-Hwa Lee
IPC分类号： G11C11/4091 , G11C5/14 , G11C7/10 , G11C5/00
CPC分类号： G11C7/1069 , G11C5/14 , G11C7/1012 , G11C7/1051
摘要： A semiconductor memory device having a data read path maintains a higher power voltage supplied to an input/output sense amplifier in the input/output path, through which data passes during a data read operation, than the voltage supplied to other circuit components in the data read path, thereby achieving a high data read speed.
摘要翻译：具有数据读取路径的半导体存储器件在数据读取操作期间保持提供给输入/输出读出放大器的输入/输出读出放大器的电压高于提供给数据中的其它电路元件的电压读取路径，从而实现高数据读取速度。

4. 发明授权

US06747908B2 Semiconductor memory device and method of selecting word line thereof 失效
标题翻译：半导体存储器件及其字线的选择方法
公开(公告)号：US06747908B2
公开(公告)日：2004-06-08
申请号：US10172314
申请日：2002-06-13
申请人： Chan-Yong Lee , Jung-Bae Lee
发明人： Chan-Yong Lee , Jung-Bae Lee
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C8/10
摘要： A semiconductor memory device includes a plurality of memory cell array blocks each including a plurality of partial blocks, a plurality of global word lines, and odd-numbered and even-numbered sub word lines corresponding to each of the plurality of the global word lines, the odd-numbered sub word lines of each of odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the previous neighboring partial blocks, the even-numbered sub word lines of each of the odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the next neighboring partial blocks, the odd-numbered sub word lines of each of even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the next neighboring partial blocks, the even-numbered sub word lines of each of the even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the previous neighboring partial blocks; and a control means for selecting sub word lines of a corresponding partial block and sub word lines of a neighboring partial block connected to the sub word lines of the corresponding partial block when the corresponding partial block is selected in response to externally applied row and column address.
摘要翻译：半导体存储器件包括多个存储单元阵列块，每个存储单元阵列块包括与多个全局字线中的每一个对应的多个部分块，多个全局字线和奇数和偶数子字线，所述多个部分块中的每个奇数部分块的奇数子字线分别连接到每个先前相邻部分块的奇数子字线，偶数子字线分别连接到每个下一个相邻部分块的偶数子字线的多个部分块中的每个奇数部分块，偶数编号的奇数子字线分别连接到下一个相邻部分块中的每一个的奇数子字线的多个部分块中的部分块，偶数的偶数子字线分别连接到每个先前相邻部分块的偶数子字线的多个部分块中的数个部分块; 以及控制装置，用于当响应于外部施加的行和列地址选择对应的部分块时，选择连接到对应的部分块的子字线的相邻部分块的相应部分块和子字线的子字线。

5. 发明申请

US20080109828A1 APPLICATION COMPONENT COMMUNICATION APPARATUS OF SCA-BASED SYSTEM AND METHOD THEREOF 有权
标题翻译：基于SCA的系统的应用组件通信设备及其方法
公开(公告)号：US20080109828A1
公开(公告)日：2008-05-08
申请号：US11743148
申请日：2007-05-02
申请人： Eun-Seon Cho , Sang-Chul Oh , Chan-Yong Lee
发明人： Eun-Seon Cho , Sang-Chul Oh , Chan-Yong Lee
IPC分类号： G06F9/44
CPC分类号： G06F9/544
摘要： An application component communication method and an apparatus using the same are provided to an SCA-based system for efficiently performing data communication between SCA-based application components by using a dynamic connection manager. The application component communication apparatus includes an application module provided in the SCA-based system and driven, an application packaged by a plurality of application components, and an application factory for generating the application and driving the application components by parsing XML files. The dynamic connection manager registers port information of each of the application components, and establishes a connection for data communication between the application components according to the port information. According to the present invention, data communication between the respective application components can be efficiently performed by using the dynamic connection manager.
摘要翻译：将应用组件通信方法及其使用方法提供给基于SCA的系统，用于通过使用动态连接管理器来有效地执行基于SCA的应用组件之间的数据通信。应用程序组件通信装置包括在基于SCA的系统中提供的应用模块并被驱动，由多个应用组件打包的应用程序以及用于生成应用程序并通过解析XML文件来驱动应用程序组件的应用程序工厂。动态连接管理器注册每个应用组件的端口信息，并根据端口信息建立应用组件之间的数据通信连接。根据本发明，可以通过使用动态连接管理器来有效地执行各个应用组件之间的数据通信。

6. 发明授权

US06636446B2 Semiconductor memory device having write latency operation and method thereof 有权
标题翻译：具有写等待时间操作的半导体存储器件及其方法
公开(公告)号：US06636446B2
公开(公告)日：2003-10-21
申请号：US10154734
申请日：2002-05-24
申请人： Chan-Yong Lee , Jung-Bae Lee
发明人： Chan-Yong Lee , Jung-Bae Lee
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G11C7/22 , G11C11/4082 , G11C2207/2218
摘要： A semiconductor memory device capable of improving common bus efficiency is disclosed. The device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal. The first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed. The second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable.
摘要翻译：公开了能够提高公共总线效率的半导体存储器件。该装置包括地址移位电路，用于响应于时钟信号将地址延迟n + m个时钟周期;控制信号发生电路，用于组合n值的列地址选通（CAS）等待时间和第一以及第二操作信号以产生控制信号，以及切换电路，用于响应于控制信号，输出延迟了从地址移位电路输出的n + m个时钟周期的地址。第一操作信号指示CAS等待时间的n值小于预定值，并且写等待时间是固定的。第二操作信号指示CAS延迟的n值等于或大于预定值，并且写入等待时间是可变的。

7. 发明授权

US08347318B2 Application component communication apparatus of SCA-based system and method thereof 有权
标题翻译：基于SCA的系统的应用组件通信设备及其方法
公开(公告)号：US08347318B2
公开(公告)日：2013-01-01
申请号：US11743148
申请日：2007-05-02
申请人： Eun-Seon Cho , Sang-Chul Oh , Chan-Yong Lee
发明人： Eun-Seon Cho , Sang-Chul Oh , Chan-Yong Lee
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F9/544
摘要： An application component communication method and an apparatus using the same are provided to an SCA-based system for efficiently performing data communication between SCA-based application components by using a dynamic connection manager. The application component communication apparatus includes an application module provided in the SCA-based system and driven, an application packaged by a plurality of application components, and an application factory for generating the application and driving the application components by parsing XML files. The dynamic connection manager registers port information of each of the application components, and establishes a connection for data communication between the application components according to the port information. According to the present invention, data communication between the respective application components can be efficiently performed by using the dynamic connection manager.
摘要翻译：将应用组件通信方法及其使用方法提供给基于SCA的系统，用于通过使用动态连接管理器来有效地执行基于SCA的应用组件之间的数据通信。应用程序组件通信装置包括在基于SCA的系统中提供的应用模块并被驱动，由多个应用组件打包的应用程序以及用于生成应用程序并通过解析XML文件来驱动应用程序组件的应用程序工厂。动态连接管理器注册每个应用组件的端口信息，并根据端口信息建立应用组件之间的数据通信连接。根据本发明，可以通过使用动态连接管理器来有效地执行各个应用组件之间的数据通信。

8. 发明授权

US07486119B2 Delay-locked loop circuit with variable bias voltages and method of clock synchronization for a semiconductor memory device 有权
标题翻译：具有可变偏置电压的延迟锁定环路电路和半导体存储器件的时钟同步方法
公开(公告)号：US07486119B2
公开(公告)日：2009-02-03
申请号：US11481518
申请日：2006-07-06
申请人： Chan-Yong Lee
发明人： Chan-Yong Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/023 , G11C2207/2227 , H03L7/0802 , H03L7/0891
摘要： A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a standby mode and an active mode. The delay-locked loop is configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal. The internal clock signal is synchronized with an external clock signal.
摘要翻译：一种延迟锁定环路，包括可变电压发生器和延迟锁定环路。可变电压发生器被配置为响应待机信号产生可变偏置电压信号。可变偏置电压信号根据操作模式具有不同的电压电平。操作模式包括待机模式和活动模式。延迟锁定环路被配置为响应待机信号和可变偏置电压信号产生内部时钟信号。内部时钟信号与外部时钟信号同步。

9. 发明申请

US20150021795A1 Water Leakage Preventing Humidification Apparatus 审中-公开
标题翻译：防漏加湿装置漏水
公开(公告)号：US20150021795A1
公开(公告)日：2015-01-22
申请号：US14381101
申请日：2012-12-27
申请人： Jun-Hyoung Bae , Kyung-Mi Lee , Chan-Yong Lee
发明人： Jun-Hyoung Bae , Kyung-Mi Lee , Chan-Yong Lee
IPC分类号： F24F13/20 , F24F6/00
CPC分类号： F24F6/00 , F16K15/02 , F16K15/18 , F24F2006/008
摘要： There is provided a water leakage preventing humidification apparatus including: a housing; a water tank installed in the housing and storing water for humidification; a water bottle having a water guide unit having an outlet formed therein to allow water to flow out therefrom, and installed in the water tank to provide water for humidification to the water tank; an installation part disposed in the water tank and having a confinement water formed to surround at least a portion of the circumference of the water guide unit of the water bottle and a water tank input hole formed on one end of the bottom surface along which water flowing out through the outlet flows and communicating with the water tank; and a humidification unit provided to perform humidification with water stored in the water tank.
摘要翻译：本发明提供一种防漏湿加湿装置，包括：壳体; 一个安装在外壳中的水箱，储存加湿用水; 具有导水单元的水瓶，其具有形成在其中的出口，以允许水从其中流出，并安装在水箱中，以向水箱提供加湿用水; 安装部，设置在水箱中，并具有形成为围绕水瓶的导水单元的圆周的至少一部分的限制水，以及形成在底面的一端上的水箱输入孔，水流入通过出口流出并与水箱连通; 以及加湿单元，用于对存储在水箱中的水进行加湿。

10. 发明申请

US20070018702A1 Delay-locked loop circuit with variable bias voltages and method of clock synchronization for a semiconductor memory device 有权
标题翻译：具有可变偏置电压的延迟锁定环路电路和半导体存储器件的时钟同步方法
公开(公告)号：US20070018702A1
公开(公告)日：2007-01-25
申请号：US11481518
申请日：2006-07-06
申请人： Chan-Yong Lee
发明人： Chan-Yong Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/023 , G11C2207/2227 , H03L7/0802 , H03L7/0891
摘要： A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a standby mode and an active mode. The delay-locked loop is configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal. The internal clock signal is synchronized with an external clock signal.
摘要翻译：一种延迟锁定环路，包括可变电压发生器和延迟锁定环路。可变电压发生器被配置为响应待机信号产生可变偏置电压信号。可变偏置电压信号根据操作模式具有不同的电压电平。操作模式包括待机模式和活动模式。延迟锁定环路被配置为响应待机信号和可变偏置电压信号产生内部时钟信号。内部时钟信号与外部时钟信号同步。

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