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71. 发明授权

US08717801B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08717801B2
公开(公告)日：2014-05-06
申请号：US13195417
申请日：2011-08-01
申请人： Hiroshi Maejima , Koji Hosono
发明人： Hiroshi Maejima , Koji Hosono
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A memory-cell array that includes a first line, a second line intersecting the first line, and a memory cell including a variable resistive element provided in the intersection of the first and the second lines; a data-write unit configured to apply a voltage pulse to the memory cell through the first and the second lines, the voltage pulse to set and/or reset data; and a detector unit configured to compare a cell current that flows through the memory cell by the voltage pulse at the time of setting and/or resetting the data with a reference current generated from the initial value of the cell current, and to control the data-write unit in accordance with a result of comparison.
摘要翻译：包括第一行，与第一行相交的第二行的存储单元阵列和包括设置在第一和第二行的交叉点中的可变电阻元件的存储单元; 数据写入单元，被配置为通过第一和第二线路向存储器单元施加电压脉冲，电压脉冲以设置和/或复位数据; 以及检测器单元，被配置为将通过存储器单元流动的单元电流与在从单元电流的初始值生成的参考电流进行设置和/或重置数据时的电压脉冲进行比较，并且控制数据根据比较结果写入单元。

72. 发明申请

US20130301334A1 METHODS, ARTICLES AND DEVICES FOR PULSE ADJUSTMENTS TO PROGRAM A MEMORY CELL 有权
标题翻译：用于脉冲调整以编程存储器单元的方法，文章和设备
公开(公告)号：US20130301334A1
公开(公告)日：2013-11-14
申请号：US13466851
申请日：2012-05-08
申请人： Alessio Spessot , Paolo Fantini , Massimo Ferro
发明人： Alessio Spessot , Paolo Fantini , Massimo Ferro
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0066 , G11C2013/0076 , G11C2013/0083 , G11C2013/0092
摘要： Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.
摘要翻译：本文公开的实施例可以涉及调整用于一个或多个存储器单元的编程脉冲的方面，例如至少部分地基于一个或多个存储器单元的一个或多个检测到的编程电阻值。

73. 发明申请

US20130250657A1 System and Method for Writing Data to an RRAM Cell 审中-公开
标题翻译：将数据写入RRAM单元的系统和方法
公开(公告)号：US20130250657A1
公开(公告)日：2013-09-26
申请号：US13789543
申请日：2013-03-07
申请人： Rambus Inc.
发明人： Brent Steven Haukness , Mark D. Kellam , Gary B. Bronner , Craig Hampel
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/79
摘要： A resistive RAM device includes a bit line, a word line, an RRAM cell coupled to the word line and to the bit line, a write driver and a disable circuit. The write driver is coupled to the bit line. The disable circuit stops a write operation performed by the write driver on a respective RRAM cell when a predefined condition on the bit line is achieved. The predefined condition depends on a mode of operation of the RRAM cell.
摘要翻译：电阻RAM装置包括位线，字线，耦合到字线和位线的RRAM单元，写驱动器和禁止电路。写驱动器耦合到位线。当实现位线上的预定义条件时，禁止电路在相应的RRAM单元上停止由写入驱动器执行的写入操作。预定义条件取决于RRAM单元的操作模式。

74. 发明授权

US08503219B2 Programmable resistance memory with feedback control 有权
标题翻译：具有反馈控制的可编程电阻存储器
公开(公告)号：US08503219B2
公开(公告)日：2013-08-06
申请号：US13158531
申请日：2011-06-13
申请人： Ward Parkinson
发明人： Ward Parkinson
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0066 , G11C2013/0078 , G11C2013/0092
摘要： A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell.
摘要翻译：可编程电阻存储器采用反馈控制电路来调节提供给选定的可编程电阻存储元件的编程电流。可编程电阻存储器可以是相变存储器。反馈控制电路监视和控制用于编程存储器单元的电流脉冲的特性。

75. 发明授权

US08391052B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08391052B2
公开(公告)日：2013-03-05
申请号：US13043736
申请日：2011-03-09
申请人： Fumihiro Kono
发明人： Fumihiro Kono
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0016 , G11C13/0061 , G11C13/0069 , G11C2013/0066 , G11C2013/0076 , G11C2013/0083 , G11C2013/0092 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/147
摘要： A nonvolatile semiconductor memory device includes a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the second lines, each of the memory cells being configured from a variable resistor operative to store a resistance value of the variable resistor as data in a nonvolatile manner. A voltage supply circuit applies a certain voltage to the memory cells via the first lines and the second lines during writing data to the memory cells or forming of the memory cells. A detection circuit detects a change of the resistance value of the variable resistor in the memory cell during application of the certain voltage to the memory cells and outputs the detected change of the resistance value of the variable resistor as detection information. An output circuit outputs to external at least a portion of the detection information outputted from the detection circuit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，所述存储单元阵列包括多个第一线，多条第二线与所述第一线相交，以及多个电可重写存储单元，设置在所述第一线的每个交点处线路和第二线路，每个存储器单元由可变电阻器构成，可变电阻器用于以非易失性方式存储可变电阻器的电阻值作为数据。电压电路在将数据写入存储单元或形成存储单元时，经由第一线和第二线向存储单元施加一定电压。检测电路检测在向存储单元施加一定电压期间存储单元中的可变电阻器的电阻值的变化，并输出检测到的可变电阻器的电阻值的变化作为检测信息。输出电路向外部输出从检测电路输出的检测信息的至少一部分。

76. 发明申请

US20120320660A1 WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：US20120320660A1
公开(公告)日：2012-12-20
申请号：US13592224
申请日：2012-08-22
申请人： Hagop NAZARIAN , Sung Hyun Jo
发明人： Hagop NAZARIAN , Sung Hyun Jo
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

77. 发明申请

US20120026778A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120026778A1
公开(公告)日：2012-02-02
申请号：US13187891
申请日：2011-07-21
申请人： Hiroshi MAEJIMA
发明人： Hiroshi MAEJIMA
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0066 , G11C2013/0083
摘要： A semiconductor memory device includes: a memory cell array including multiple first lines, multiple second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and including variable resistive elements; and a control circuit which controls resistance values of the variable resistive elements in a way that a cell voltage is applied to the memory cell arranged at an intersection between a selected first line and a selected second line by applying first and second voltages to the selected first and second lines, respectively. The control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, and a pulsing voltage as the second voltage to the selected second line. The second voltage includes a voltage pulse which is raised from a second initial voltage to turn the memory cell into a non-selected state to a voltage to turn the memory cell into a selected state, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising with a change in the first voltage reaches a predetermined compliance current.
摘要翻译：半导体存储器件包括：存储单元阵列，包括多个第一线，与第一线交叉的多个第二线，以及布置在第一线和第二线之间的交叉点处并包括可变电阻元件的存储单元; 以及控制电路，其以将单元电压施加到布置在所选择的第一线路和所选择的第二线路之间的交叉点处的存储器单元的方式来控制可变电阻元件的电阻值，所述方法是将第一和第二电压施加到所选择的第一和第二行。控制电路将从第一初始电压逐渐升高或降低的电压作为第一电压施加到所选择的第一线，并且将脉冲电压作为第二电压施加到所选择的第二线。第二电压包括从第二初始电压升高的电压脉冲，将存储单元转换为非选择状态，将存储单元转换成选择状态的电压，保持在升高的电压，从而使单元当存储单元的电压随着第一电压的变化而升高的单元电流达到预定的顺从电流时，电流流入存储单元，并且降低到第二初始电压。

78. 发明授权

US08098512B2 Reading phase change memories 有权
标题翻译：阅读相变记忆
公开(公告)号：US08098512B2
公开(公告)日：2012-01-17
申请号：US13072911
申请日：2011-03-28
申请人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
发明人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译：可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。在某些情况下，较高的电流可能会改善性能。由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。

79. 发明申请

US20110299320A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110299320A1
公开(公告)日：2011-12-08
申请号：US13043736
申请日：2011-03-09
申请人： Fumihiro KONO
发明人： Fumihiro KONO
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0016 , G11C13/0061 , G11C13/0069 , G11C2013/0066 , G11C2013/0076 , G11C2013/0083 , G11C2013/0092 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/147
摘要： A nonvolatile semiconductor memory device includes a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the second lines, each of the memory cells being configured from a variable resistor operative to store a resistance value of the variable resistor as data in a nonvolatile manner. A voltage supply circuit applies a certain voltage to the memory cells via the first lines and the second lines during writing data to the memory cells or forming of the memory cells. A detection circuit detects a change of the resistance value of the variable resistor in the memory cell during application of the certain voltage to the memory cells and outputs the detected change of the resistance value of the variable resistor as detection information. An output circuit outputs to external at least a portion of the detection information outputted from the detection circuit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，所述存储单元阵列包括多个第一线，多条第二线与所述第一线相交，以及多个电可重写存储单元，设置在所述第一线的每个交点处线路和第二线路，每个存储器单元由可变电阻器构成，可变电阻器用于以非易失性方式存储可变电阻器的电阻值作为数据。电压电路在将数据写入存储单元或形成存储单元时，经由第一线和第二线向存储单元施加一定电压。检测电路检测在向存储单元施加一定电压期间存储单元中的可变电阻器的电阻值的变化，并输出检测到的可变电阻器的电阻值的变化作为检测信息。输出电路向外部输出从检测电路输出的检测信息的至少一部分。

80. 发明申请

US20110157958A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20110157958A1
公开(公告)日：2011-06-30
申请号：US12885815
申请日：2010-09-20
申请人： Takahiko SASAKI
发明人： Takahiko SASAKI
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0061 , G11C13/0069 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device comprises a memory cell array and a control circuit. The control circuit applies a certain potential difference to a selected one of the memory cells. The control circuit comprises a current mirror circuit, a reference current generating circuit, and a detecting circuit. The current mirror circuit produces a mirror current having a current value identical to that of a cell current flowing in the selected one of the memory cells. The reference current generating circuit produces a reference current, the reference current having a current value that differs from the current value of the mirror current by a certain current value. The detecting circuit detects transition of a resistance state of the selected one of the memory cells based on a magnitude relation of the mirror current and the reference current.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列和控制电路。控制电路向选定的一个存储单元施加一定的电位差。控制电路包括电流镜电路，参考电流产生电路和检测电路。电流镜电路产生具有与在选定的一个存储单元中流动的单电池电流相同的电流值的反射镜电流。参考电流产生电路产生参考电流，该参考电流的电流值与镜电流的当前值相差一定电流值。检测电路基于反射镜电流和参考电流的大小关系来检测所选择的一个存储单元的电阻状态的转变。

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