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1. 发明授权

US08345466B2 Nonvolatile semiconductor memory device adjusting voltage of lines in a memory cell array 有权
标题翻译：非易失性半导体存储器件调整存储单元阵列中的线的电压
公开(公告)号：US08345466B2
公开(公告)日：2013-01-01
申请号：US12849407
申请日：2010-08-03
申请人： Hiroshi Maejima , Koji Hosono
发明人： Hiroshi Maejima , Koji Hosono
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C2013/0083 , G11C2213/56 , G11C2213/72
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array including: a plurality of first lines; a plurality of second lines intersecting the first lines; and a plurality of memory cells each including a variable resistance element disposed at the intersection of the first and second lines and configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a control unit configured to detect an amount of a current flowing through the first line when a memory cell is accessed, and adjust the voltage of the first or second line based on the amount of the current.
摘要翻译：根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一线; 与第一线相交的多个第二线; 以及多个存储单元，每个存储单元包括设置在第一和第二行的交叉点处的可变电阻元件，并且被配置为以非易失性方式存储作为数据的电可重写电阻值;以及控制单元，被配置为检测电流量当访问存储器单元时流过第一行，并且基于电流量来调整第一行或第二行的电压。

2. 发明申请

US20110032746A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110032746A1
公开(公告)日：2011-02-10
申请号：US12849407
申请日：2010-08-03
申请人： Hiroshi Maejima , Koji Hosono
发明人： Hiroshi Maejima , Koji Hosono
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C2013/0083 , G11C2213/56 , G11C2213/72
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array including: a plurality of first lines; a plurality of second lines intersecting the first lines; and a plurality of memory cells each including a variable resistance element disposed at the intersection of the first and second lines and configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a control unit configured to detect an amount of a current flowing through the first line when a memory cell is accessed, and adjust the voltage of the first or second line based on the amount of the current.
摘要翻译：根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一线; 与第一线相交的多个第二线; 以及多个存储单元，每个存储单元包括设置在第一和第二行的交叉点处的可变电阻元件，并且被配置为以非易失性方式存储作为数据的电可重写电阻值;以及控制单元，被配置为检测电流量当访问存储器单元时流过第一行，并且基于电流量来调整第一行或第二行的电压。

3. 发明申请

US20060023512A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060023512A1
公开(公告)日：2006-02-02
申请号：US11193456
申请日：2005-08-01
申请人： Hiroshi Maejima , Koji Hosono
发明人： Hiroshi Maejima , Koji Hosono
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： A semiconductor memory device is disclosed, which includes a plurality of NAND cells each comprising a plurality of series-connected memory cell transistors, and a drain-side select transistor and a source-side select transistor connected to a drain-side end and a source-side end of the series-connected memory cell transistors, respectively, a source line commonly connected to the source-side select transistors in the plurality of NAND cells, a first discharge circuit which is connected between the source line and a reference potential and whose conduction/non-conduction is controlled by a first control signal, and a second discharge circuit which is connected between the source line and the reference potential and whose conduction/non-conduction is controlled by a second control signal different from the first control signal.
摘要翻译：公开了一种半导体存储器件，其包括多个NAND单元，每个NAND单元包括多个串联存储单元晶体管，漏极侧选择晶体管和源极侧选择晶体管连接到漏极侧端和源极串联的存储单元晶体管的端部分别是与多个NAND单元中的源极侧选择晶体管共同连接的源极线，连接在源极线和参考电位之间的第一放电电路，导通/非导通由第一控制信号控制，第二放电电路连接在源极线和参考电位之间，其导通/非导通由与第一控制信号不同的第二控制信号控制。

4. 发明授权

US08391047B2 Method of executing a forming operation to variable resistance element 有权
标题翻译：对可变电阻元件执行成形操作的方法
公开(公告)号：US08391047B2
公开(公告)日：2013-03-05
申请号：US12721092
申请日：2010-03-10
申请人： Hiroshi Maejima , Koji Hosono
发明人： Hiroshi Maejima , Koji Hosono
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C13/0004 , G11C13/0064 , G11C29/028 , G11C2013/0083 , G11C2013/0088 , G11C2029/0403
摘要： A method of executing a forming operation to a variable resistance element to render a resistance value of the variable resistance element capable of transition, the variable resistance element being included in a memory cell connected between a first wiring and a second wiring and changing the resistance value by electrical control, comprises applying a voltage required to execute the forming operation to the variable resistance element between the first and second wirings and changing the first wiring to a floating state.
摘要翻译：一种向可变电阻元件执行形成操作以使可变电阻元件能够转变的电阻值的方法，所述可变电阻元件包括在连接在第一布线和第二布线之间并改变电阻值的存储单元中通过电气控制，包括向第一和第二布线之间的可变电阻元件施加执行成形操作所需的电压并将第一布线改变为浮动状态。

5. 发明授权

US08085576B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08085576B2
公开(公告)日：2011-12-27
申请号：US12710661
申请日：2010-02-23
申请人： Koji Hosono , Hiroshi Maejima
发明人： Koji Hosono , Hiroshi Maejima
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2013/009 , G11C2213/72
摘要： A semiconductor memory device comprises: a memory cell array having memory cells disposed at a crossing-point of a plurality of first lines and a plurality of second lines and a control circuit configured to apply a first voltage to selected one or more of the first lines, and to apply a second voltage having a value smaller than the first voltage to selected one of the second lines, such that a certain potential difference is applied to selected one or more of the memory cells. The control circuit adjusts the second voltage based on a position of the selected one or more of the memory cells within the memory cell array and a number of the selected one or more of the memory cells on which an operation is simultaneously executed, during application of the potential difference to the selected one or more of the memory cells.
摘要翻译：半导体存储器件包括：存储单元阵列，其具有设置在多个第一线的交叉点处的存储单元和多条第二线;以及控制电路，被配置为向所选择的一条或多条第一条线施加第一电压并且将具有小于第一电压的值的第二电压施加到所选择的第二行中的一个，使得对所选择的一个或多个存储器单元施加一定的电位差。控制电路根据存储单元阵列内所选择的一个或多个存储器单元的位置以及在其中同时执行操作的所选择的一个或多个存储器单元的数量来调整第二电压，与所选择的一个或多个存储器单元的电位差。

6. 发明授权

US07835181B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07835181B2
公开(公告)日：2010-11-16
申请号：US11839341
申请日：2007-08-15
申请人： Hiroshi Maejima , Koji Hosono
发明人： Hiroshi Maejima , Koji Hosono
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： A semiconductor memory device is disclosed, which includes a plurality of NAND cells each comprising a plurality of series-connected memory cell transistors, and a drain-side select transistor and a source-side select transistor connected to a drain-side end and a source-side end of the series-connected memory cell transistors, respectively, a source line commonly connected to the source-side select transistors in the plurality of NAND cells, a first discharge circuit which is connected between the source line and a reference potential and whose conduction/non-conduction is controlled by a first control signal, and a second discharge circuit which is connected between the source line and the reference potential and whose conduction/ non-conduction is controlled by a second control signal different from the first control signal.
摘要翻译：公开了一种半导体存储器件，其包括多个NAND单元，每个NAND单元包括多个串联存储单元晶体管，漏极侧选择晶体管和源极侧选择晶体管连接到漏极侧端和源极串联的存储单元晶体管的端部分别是与多个NAND单元中的源极侧选择晶体管共同连接的源极线，连接在源极线和参考电位之间的第一放电电路，导通/非导通由第一控制信号控制，第二放电电路连接在源极线和参考电位之间，其导通/非导通由与第一控制信号不同的第二控制信号控制。

7. 发明申请

US20100208510A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20100208510A1
公开(公告)日：2010-08-19
申请号：US12707298
申请日：2010-02-17
申请人： Koji HOSONO , Hiroshi Maejima
发明人： Koji HOSONO , Hiroshi Maejima
IPC分类号： G11C11/00 , G11C29/00
CPC分类号： G11C13/0011 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C29/025 , G11C29/83 , G11C2013/009 , G11C2213/72
摘要： A semiconductor memory device comprises: a memory cell array having memory cells disposed at a crossing-point of a plurality of first lines and a plurality of second lines; and a control circuit configured to apply a first voltage to selected one of the first lines, and to apply a second voltage to selected one of the second lines. The control circuit comprises: a first isolation latch circuit configured to set the first lines to a floating state; and a second isolation latch circuit configured to set the second lines to the floating state. During a forming operation, the first and second isolation latch circuits set one of the first lines and one of the second lines to which a defective memory cell is connected to the floating state, the defective memory cell being one of the memory cells that allows a current to flow due to application of a voltage.
摘要翻译：半导体存储器件包括：存储单元阵列，具有设置在多个第一线和多条第二线的交叉点处的存储单元; 以及控制电路，被配置为将第一电压施加到所选择的第一行中的一个，并且将第二电压施加到所选择的第二行中的一个。所述控制电路包括：第一隔离锁存电路，被配置为将所述第一线路设置为浮置状态; 以及第二隔离锁存电路，被配置为将第二线路设置为浮置状态。在成形操作期间，第一和第二隔离锁存电路将缺陷存储单元连接到浮动状态的第一行和第二行中的一个设置为有缺陷的存储单元，电流由于施加电压而流动。

8. 发明申请

US20100046275A1 NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND DATA PROGRAMMING METHOD THEREOF 有权
标题翻译：非易失性半导体存储设备及其数据编程方法
公开(公告)号：US20100046275A1
公开(公告)日：2010-02-25
申请号：US12544276
申请日：2009-08-20
申请人： Koji Hosono , Hiroshi Maejima , Yuri Terada
发明人： Koji Hosono , Hiroshi Maejima , Yuri Terada
IPC分类号： G11C7/00 , G11C11/00 , G11C5/02
CPC分类号： G11C5/02 , G11C5/063 , G11C8/10
摘要： The semiconductor storage apparatus includes a memory cell array including memory cells each having a rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires, and a control circuit configured to control charging to the first wire. The control circuit charges the first wire connected to a selected memory cell up to a first potential, and then set the first wire in a floating state. Then it charges another first wire adjacent to the first wire connected to the selected memory cell to a second potential. The potential of the first wire connected to the selected memory cell is thereby caused to rise to a third potential by coupling.
摘要翻译：半导体存储装置包括：存储单元阵列，具有各自具有串联连接的整流元件和可变电阻元件的存储单元，所述存储单元配置在多个第一布线和多个第二布线的交叉部分;以及控制单元电路被配置为控制对第一线的充电。控制电路将连接到所选存储单元的第一线充电至第一电位，然后将第一导线设置为浮置状态。然后，将连接到所选择的存储器单元的第一引线附近的另一个第一导线充电到第二电位。因此，连接到所选择的存储单元的第一线的电位通过耦合而上升到第三电位。

9. 发明授权

US07505311B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07505311B2
公开(公告)日：2009-03-17
申请号：US11840525
申请日：2007-08-17
申请人： Hiroshi Maejima , Koji Hosono
发明人： Hiroshi Maejima , Koji Hosono
IPC分类号： G11C11/24 , G11C7/12
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26
摘要： A semiconductor memory device includes a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of the memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein the bit line control circuit comprises a first transistor and a second transistor with a breakdown voltage higher than that of the first transistor, the second transistor being disposed between the first transistor and a bit line in the memory cell array to be serially connected to the first transistor, and wherein a connection node between the first and second transistors is fixed in potential at a data erase time.
摘要翻译：一种半导体存储器件包括其中布置有电可重写和非易失性存储单元的存储单元阵列，以及连接到存储单元阵列的位线的位线控制电路，以根据操作模式控制和检测位线电压，其中所述位线控制电路包括具有比所述第一晶体管的击穿电压高的击穿电压的第一晶体管和第二晶体管，所述第二晶体管设置在所述第一晶体管和所述存储单元阵列中的位线之间以串联连接到第一晶体管，并且其中第一和第二晶体管之间的连接节点在数据擦除时间被固定为电位。

10. 发明授权

US07259985B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07259985B2
公开(公告)日：2007-08-21
申请号：US11245195
申请日：2005-10-07
申请人： Hiroshi Maejima , Koji Hosono
发明人： Hiroshi Maejima , Koji Hosono
IPC分类号： G11C11/24 , G11C7/12
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26
摘要： A semiconductor memory device includes a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of the memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein the bit line control circuit comprises a first transistor and a second transistor with a breakdown voltage higher than that of the first transistor, the second transistor being disposed between the first transistor and a bit line in the memory cell array to be serially connected to the first transistor, and wherein a connection node between the first and second transistors is fixed in potential at a data erase time.
摘要翻译：一种半导体存储器件包括其中布置有电可重写和非易失性存储单元的存储单元阵列，以及连接到存储单元阵列的位线的位线控制电路，以根据操作模式控制和检测位线电压，其中所述位线控制电路包括具有比所述第一晶体管的击穿电压高的击穿电压的第一晶体管和第二晶体管，所述第二晶体管设置在所述第一晶体管和所述存储单元阵列中的位线之间以串联连接到第一晶体管，并且其中第一和第二晶体管之间的连接节点在数据擦除时间被固定为电位。

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