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71. 发明授权

US08269784B2 Processor architecture for executing wide transform slice instructions 有权
标题翻译：用于执行宽变换片指令的处理器架构
公开(公告)号：US08269784B2
公开(公告)日：2012-09-18
申请号：US13354214
申请日：2012-01-19
申请人： Craig Hansen , John Moussouris , Alexia Massalin
发明人： Craig Hansen , John Moussouris , Alexia Massalin
IPC分类号： G06T1/00 , G06F13/14 , G06F15/00 , G06F7/38
CPC分类号： G06F9/30014 , G06F9/30007 , G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/34 , G06F9/3824 , G06F9/383 , G06F9/3885 , G06F12/0886
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及操作数的大小和形状。此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

72. 发明授权

US08261048B2 Optional function multi-function instruction in an emulated computing environment 有权
标题翻译：模拟计算环境中的可选功能多功能指令
公开(公告)号：US08261048B2
公开(公告)日：2012-09-04
申请号：US13324396
申请日：2011-12-13
申请人： Shawn D. Lundvall , Ronald M. Smith, Sr. , Phil Chi-Chung Yeh
发明人： Shawn D. Lundvall , Ronald M. Smith, Sr. , Phil Chi-Chung Yeh
IPC分类号： G06F9/00
CPC分类号： G06F9/45504 , G06F9/30007 , G06F9/30018 , G06F9/30094 , G06F9/3017 , G06F9/30181 , G06F9/342 , G06F21/72 , H04L9/08
摘要： A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.
摘要翻译：一种用于在仿真计算机系统中执行多功能指令的方法，系统和程序产品，其通过多功能指令来指定能力查询或执行一个或多个可选功能的选定功能，其中所选功能是安装的可选功能，其中能力查询确定在计算机系统上安装一个或多个可选功能的哪些可选功能。

73. 发明授权

US08145804B2 Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor 有权
标题翻译：用于传送数据以维持双端处理器中优选插槽位置的系统和方法
公开(公告)号：US08145804B2
公开(公告)日：2012-03-27
申请号：US12563756
申请日：2009-09-21
申请人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
发明人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
IPC分类号： G06F13/28
CPC分类号： G06F9/30007 , G06F9/3824
摘要： A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
摘要翻译：一种具有多个处理元件的双端式多处理器系统，每个处理单元包括处理器核心，本地存储器和存储器流控制器。存储器流控制器在本地存储器和处理元件外部的数据源之间传送数据。如果处理元件和数据源实现具有相同字节数的数据表示，则每个多字数据行以与数据源中相同的字顺序存储在本地存储器中。如果处理元件和数据源实现具有不同端点的数据表示，则当数据在本地存储器和数据源之间传送时，每个多字数据行的字被转置。处理元件可以包括用于添加双字的电路，其中，根据数据行中的字是否被转置，电路可以交替地将位从第一个字运送到第二个字，反之亦然。

74. 发明授权

US08132022B2 Apparatus and method for employing configurable hash algorithms 有权
标题翻译：用于采用可配置散列算法的装置和方法
公开(公告)号：US08132022B2
公开(公告)日：2012-03-06
申请号：US12977803
申请日：2010-12-23
申请人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
IPC分类号： G06F12/14 , G06F9/30 , H04L9/32 , H04K1/00
CPC分类号： H04L9/3239 , G06F9/30007 , G06F9/30065 , G06F9/30185 , G06F9/3895 , G06F21/64 , G06F21/72 , H04L9/0643 , H04L2209/125 , H04L2209/60
摘要： A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit disposed within execution logic, executing the one of the hash operations. The executing includes first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.
摘要翻译：一种用于执行散列操作的方法，包括：接收作为应用程序的一部分的散列指令，其中所述散列指令规定所述散列操作之一和多个散列算法之一; 将所述散列指令转换成第一多个微指令和第二多个微指令; 并且经由布置在执行逻辑内的哈希单元，执行所述散列操作之一。所述执行包括首先执行所述散列单元内的所述第一多个微指令以产生输出数据; 第二执行x86整数单元内的第二多个微指令，与第一次执行一起执行以测试标志寄存器中的位，更新文本指针寄存器，以及在执行散列操作期间处理中断; 以及在允许待决中断进行之前将相应的中间散列值存储到存储器。

75. 发明授权

US08103860B2 Optional function multi-function instruction 有权
标题翻译：可选功能多功能指令
公开(公告)号：US08103860B2
公开(公告)日：2012-01-24
申请号：US11692382
申请日：2007-03-28
申请人： Shawn D. Lundvall , Ronald M. Smith, Sr. , Phil Chi-Chung Yeh
发明人： Shawn D. Lundvall , Ronald M. Smith, Sr. , Phil Chi-Chung Yeh
IPC分类号： G06F9/00
CPC分类号： G06F9/45504 , G06F9/30007 , G06F9/30018 , G06F9/30094 , G06F9/3017 , G06F9/30181 , G06F9/342 , G06F21/72 , H04L9/08
摘要： A method, system and program product for executing a multi-function instruction in a computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.
摘要翻译：一种用于在计算机系统中执行多功能指令的方法，系统和程序产品，所述方法，系统和程序产品通过经由所述多功能指令来指定一个或多个可选功能的所选功能的能力查询或执行，其中所选择的功能是安装的可选功能，其中所述能力查询确定所述一个或多个可选功能的哪些可选功能被安装在所述计算机系统上。

76. 发明申请

US20110302394A1 SYSTEM AND METHOD FOR PROCESSING REGULAR EXPRESSIONS USING SIMD AND PARALLEL STREAMS 审中-公开
标题翻译：使用SIMD和并行流处理正则表达式的系统和方法
公开(公告)号：US20110302394A1
公开(公告)日：2011-12-08
申请号：US12795874
申请日：2010-06-08
申请人： GREGORY F. RUSSELL , Valentina Salapura , Daniele P. Scarpazza
发明人： GREGORY F. RUSSELL , Valentina Salapura , Daniele P. Scarpazza
IPC分类号： G06F9/302
CPC分类号： G06F9/3887 , G06F9/30007
摘要： A system and method for performing regular expression computations includes loading a plurality of input values corresponding to one or more input streams as elements of a vector register implemented on programmable storage media. New state indexes are computed using the input values, and current state values corresponding to different automata by using single instruction, multiple data (SIMD) vector operations. New state values associated with the different automata are determined using the new state indexes to look up new state values such that state transitions for a plurality of regular expressions are processed concurrently.
摘要翻译：用于执行正则表达式计算的系统和方法包括将对应于一个或多个输入流的多个输入值作为在可编程存储介质上实现的向量寄存器的元素进行加载。通过使用单指令，多数据（SIMD）向量运算，使用输入值和与不同自动机对应的当前状态值计算新状态指标。使用新的状态索引来确定与不同自动机相关联的新状态值以查找新的状态值，使得多个正则表达式的状态转换被并发处理。

77. 发明授权

US07949130B2 Architecture and instruction set for implementing advanced encryption standard (AES) 有权
标题翻译：实现高级加密标准（AES）的体系结构和指令集
公开(公告)号：US07949130B2
公开(公告)日：2011-05-24
申请号：US11648434
申请日：2006-12-28
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/28 , G06F15/00 , G06F12/14
CPC分类号： H04L9/0631 , G06F9/30007 , G06F21/602 , H04L9/14 , H04L2209/24
摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
摘要翻译：提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

78. 发明授权

US07948496B2 Processor architecture with wide operand cache 有权
标题翻译：具有宽操作数缓存的处理器架构
公开(公告)号：US07948496B2
公开(公告)日：2011-05-24
申请号：US11982051
申请日：2007-10-31
申请人： Craig Hansen , John Moussouris , Alexia Massalin
发明人： Craig Hansen , John Moussouris , Alexia Massalin
IPC分类号： G06T1/00 , G06T15/00 , G06F15/00
CPC分类号： G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及操作数的大小和形状。此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

79. 发明授权

US07932911B2 Processor for executing switch and translate instructions requiring wide operands 有权
标题翻译：用于执行切换和转换需要广泛操作数的指令的处理器
公开(公告)号：US07932911B2
公开(公告)日：2011-04-26
申请号：US11982171
申请日：2007-10-31
申请人： Craig Hansen , John Moussouris , Alexia Massalin
发明人： Craig Hansen , John Moussouris , Alexia Massalin
IPC分类号： G06T1/00 , G06F15/76 , G06F7/38
CPC分类号： G06F12/02 , G06F9/30007 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/383 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及操作数的大小和形状。此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

80. 发明授权

US07844053B2 Microprocessor apparatus and method for performing block cipher cryptographic functions 有权
标题翻译：用于执行块密码加密功能的微处理器装置和方法
公开(公告)号：US07844053B2
公开(公告)日：2010-11-30
申请号：US10730167
申请日：2003-12-05
申请人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
发明人： Thomas A. Crispin , G. Glenn Henry , Terry Parks
IPC分类号： G06F15/76
CPC分类号： G06F9/30003 , G06F9/30007 , G06F9/30047 , G06F9/30065 , G06F9/30087 , G06F9/3017 , G06F9/30178 , G06F9/3885 , G06F21/602 , G06F21/6245 , G06F21/72 , H04L9/06
摘要： A microprocessor apparatus is provided, for performing a cryptographic operation. The microprocessor apparatus includes an x86-compatible microprocessor that has fetch logic, a cryptography unit, and an integer unit. The fetch logic is configured to fetch an application program from memory for execution by the x86-compatible microprocessor. The application program includes an atomic instruction that directs the x86-compatible microprocessor to perform the cryptographic operation. The atomic instruction has and opcode field and a repeat prefix field. The opcode field prescribes that the device accomplish the cryptographic operation as further specified within a control word stored in a memory. The repeat prefix field is coupled to the opcode field. The repeat prefix field indicates that the cryptographic operation prescribed by the atomic instruction is to be accomplished on a plurality of blocks of input data.
摘要翻译：提供了一种用于执行密码操作的微处理器装置。微处理器装置包括具有取指逻辑的x86兼容微处理器，加密单元和整数单元。提取逻辑被配置为从存储器获取应用程序以由x86兼容的微处理器执行。应用程序包括指导x86兼容微处理器执行加密操作的原子指令。原子指令具有和操作码字段和重复前缀字段。操作码字段规定设备完成在存储在存储器中的控制字中进一步指定的加密操作。重复前缀字段耦合到操作码字段。重复前缀字段指示由原子指令规定的加密操作将在多个输入数据块上完成。

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