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71. 发明授权

US07536560B2 Microprocessor apparatus and method for providing configurable cryptographic key size 有权
标题翻译：用于提供可配置密码密钥大小的微处理器装置和方法
公开(公告)号：US07536560B2
公开(公告)日：2009-05-19
申请号：US10826475
申请日：2004-04-16
申请人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
发明人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
IPC分类号： H04L9/06
CPC分类号： G06F9/30181 , G06F9/30003 , G06F9/30007 , G06F9/30174 , G06F9/3877 , G06F21/72 , H04L9/0631 , H04L9/0637 , H04L2209/125 , H04L2209/24
摘要： The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a microprocessor, where the size cryptographic key that is employed is programmable. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes fetch logic and execution logic. The fetch logic is disposed within a microprocessor, and receives a cryptographic instructionsingle atomic cryptographic instruction as part of an instruction flow executing on the microprocessor. The cryptographic instructionsingle atomic cryptographic instruction prescribes one of the cryptographic operations, and also one of a plurality of cryptographic key sizes. The execution logic disposed within the microprocessor and is operatively coupled to the single atomic cryptographic instruction. The execution logic executes the one of the cryptographic operations. The execution logic has a cryptographic key size controller that employs the one of a plurality of cryptographic key sizes during execution of the one of the cryptographic operations.
摘要翻译：本发明提供一种用于对微处理器内的多个输入数据块执行密码操作的装置和方法，其中使用的大小密码密钥是可编程的。在一个实施例中，提供了一种用于执行密码操作的装置。该装置包括提取逻辑和执行逻辑。提取逻辑设置在微处理器内，并且接收作为在微处理器上执行的指令流的一部分的加密指令单原子加密指令。加密指令单原子加密指令规定了密码操作之一以及多个加密密钥大小之一。执行逻辑设置在微处理器内，并且可操作地耦合到单原子加密指令。执行逻辑执行加密操作之一。执行逻辑具有加密密钥大小控制器，该加密密钥大小控制器在执行所述密码操作之一期间采用多个密码密钥大小中的一个。

72. 发明授权

US07529368B2 Apparatus and method for performing transparent output feedback mode cryptographic functions 有权
标题翻译：用于执行透明输出反馈模式加密功能的装置和方法
公开(公告)号：US07529368B2
公开(公告)日：2009-05-05
申请号：US10826745
申请日：2004-04-16
申请人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
发明人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
IPC分类号： H04J1/06
CPC分类号： G06F9/3017 , G06F9/30003 , G06F9/30007 , G06F9/30178 , G06F9/3877 , G06F21/72 , H04L9/0631 , H04L9/0637 , H04L2209/125 , H04L2209/24
摘要： An apparatus and method for performing cryptographic operations on a plurality of input data blocks. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction, OFB mode logic, and execution logic. The cryptographic instruction is received by a pipeline microprocessor as part of an application program executing on the pipeline microprocessor. The cryptographic instruction prescribes one of the cryptographic operations. The one of the cryptographic operations includes a plurality of OFB block cryptographic operations performed on a corresponding plurality of input text blocks. The OFB mode logic is operatively coupled to the cryptographic instruction. The OFB mode logic directs the pipeline microprocessor to update pointer registers and an initialization vector location for each of the plurality of CFB block cryptographic operations. The execution logic is operatively coupled to the OFB mode logic. The execution logic executes the one of the cryptographic operations.
摘要翻译：一种用于对多个输入数据块执行密码操作的装置和方法。在一个实施例中，提供了一种用于执行密码操作的装置。该装置包括密码指令，OFB模式逻辑和执行逻辑。密码指令由流水线微处理器接收，作为在流水线微处理器上执行的应用程序的一部分。加密指令规定了一种加密操作。密码操作之一包括对相应的多个输入文本块执行的多个OFB块密码操作。 OFB模式逻辑可操作地耦合到密码指令。 OFB模式逻辑指示流水线微处理器更新多个CFB块加密操作中的每一个的指针寄存器和初始化向量位置。执行逻辑可操作地耦合到OFB模式逻辑。执行逻辑执行加密操作之一。

73. 发明授权

US07529367B2 Apparatus and method for performing transparent cipher feedback mode cryptographic functions 有权
标题翻译：用于执行透明密码反馈模式密码功能的装置和方法
公开(公告)号：US07529367B2
公开(公告)日：2009-05-05
申请号：US10826428
申请日：2004-04-16
申请人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
发明人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
IPC分类号： H04K1/06
CPC分类号： H04L9/0631 , G06F9/30007 , H04L9/0637 , H04L2209/125 , H04L2209/24
摘要： An apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction, CFB mode logic, and execution logic. The cryptographic instruction is received by a pipeline microprocessor as part of an application program executing on the pipeline microprocessor. The cryptographic instruction prescribes one of the cryptographic operations. The one of the cryptographic operations includes a plurality of CFB block cryptographic operations performed on a corresponding plurality of input text blocks. The CFB mode logic is operatively coupled to the cryptographic instruction. The CFB mode logic directs the pipeline microprocessor to update pointer registers and intermediate results for each of the plurality of CFB block cryptographic operations. The execution logic is operatively coupled to the CFB mode logic. The execution logic executes the one of the cryptographic operations.
摘要翻译：一种用于对处理器内的多个输入数据块执行加密操作的装置和方法。在一个实施例中，提供了一种用于执行密码操作的装置。该装置包括密码指令，CFB模式逻辑和执行逻辑。密码指令由流水线微处理器接收，作为在流水线微处理器上执行的应用程序的一部分。加密指令规定了一种加密操作。密码操作之一包括对相应的多个输入文本块执行的多个CFB块加密操作。 CFB模式逻辑可操作地耦合到密码指令。 CFB模式逻辑指示流水线微处理器为多个CFB块加密操作中的每一个更新指针寄存器和中间结果。执行逻辑可操作地耦合到CFB模式逻辑。执行逻辑执行加密操作之一。

74. 发明申请

US20090100227A1 Processor architecture with wide operand cache 有权
标题翻译：具有宽操作数缓存的处理器架构
公开(公告)号：US20090100227A1
公开(公告)日：2009-04-16
申请号：US11982051
申请日：2007-10-31
申请人： Craig Hansen , John Moussouris , Alexia Massalin
发明人： Craig Hansen , John Moussouris , Alexia Massalin
IPC分类号： G06F12/00
CPC分类号： G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及操作数的大小和形状。此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

75. 发明申请

US20090089540A1 Processor architecture for executing transfers between wide operand memories 审中-公开
标题翻译：用于执行广泛操作数存储器之间传输的处理器架构
公开(公告)号：US20090089540A1
公开(公告)日：2009-04-02
申请号：US11982202
申请日：2007-10-31
申请人： Craig Hansen , John Moussouris , Alexia Massalin
发明人： Craig Hansen , John Moussouris , Alexia Massalin
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/30014 , G06F9/30007 , G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/32 , G06F9/34 , G06F9/3824 , G06F9/383 , G06F9/3885 , G06F12/0886
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及操作数的大小和形状。此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

76. 发明申请

US20090083498A1 Programmable processor and method with wide operations 有权
标题翻译：可编程处理器和方法具有广泛的操作
公开(公告)号：US20090083498A1
公开(公告)日：2009-03-26
申请号：US11346213
申请日：2006-02-03
申请人： Craig Hansen , John Moussouris , Alexia Massalin
发明人： Craig Hansen , John Moussouris , Alexia Massalin
IPC分类号： G06F12/00
CPC分类号： G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及操作数的大小和形状。此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

77. 发明申请

US20080201554A1 Optional Function Multi-Function Instruction 有权
标题翻译：可选功能多功能指令
公开(公告)号：US20080201554A1
公开(公告)日：2008-08-21
申请号：US11692382
申请日：2007-03-28
申请人： Shawn D. Lundvall , Ronald M. Smith , Phil Chi-Chung Yeh
发明人： Shawn D. Lundvall , Ronald M. Smith , Phil Chi-Chung Yeh
IPC分类号： G06F9/30
CPC分类号： G06F9/45504 , G06F9/30007 , G06F9/30018 , G06F9/30094 , G06F9/3017 , G06F9/30181 , G06F9/342 , G06F21/72 , H04L9/08
摘要： A method, system and program product for executing a multi-function instruction in a computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.
摘要翻译：一种用于在计算机系统中执行多功能指令的方法，系统和程序产品，所述方法，系统和程序产品通过经由所述多功能指令来指定一个或多个可选功能的所选功能的能力查询或执行，其中所选择的功能是安装的可选功能，其中所述能力查询确定所述一个或多个可选功能的哪些可选功能被安装在所述计算机系统上。

78. 发明授权

US07392400B2 Microprocessor apparatus and method for optimizing block cipher cryptographic functions 有权
标题翻译：用于优化块密码加密功能的微处理器装置和方法
公开(公告)号：US07392400B2
公开(公告)日：2008-06-24
申请号：US10800768
申请日：2004-03-15
申请人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
发明人： G. Glenn Henry , Thomas A. Crispin , Terry Parks
IPC分类号： G06F11/30
CPC分类号： G06F9/3017 , G06F9/30003 , G06F9/30007 , G06F9/30178 , G06F9/3877 , G06F21/72 , H04L9/0631 , H04L2209/125 , H04L2209/24
摘要： The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and translation logic. The cryptographic instruction is received by fetch logic in a microprocessor as part of an instruction flow. The cryptographic instruction prescribes one of the cryptographic operations. The translation logic translates the cryptographic instruction into micro instructions. The micro instructions are ordered to direct the microprocessor to load a second input text block and to execute the one of the cryptographic operations on the second input text block prior to directing the microprocessor to store an output text block corresponding to a first input text block. Consequently, the output text block is stored during execution of the one of the cryptographic operations on the second input text block.
摘要翻译：本发明提供一种用于对处理器内的多个输入数据块执行密码操作的装置和方法。在一个实施例中，提供了一种用于执行密码操作的装置。该装置包括加密指令和翻译逻辑。作为指令流的一部分，加密指令由微处理器中的提取逻辑接收。加密指令规定了一种加密操作。翻译逻辑将加密指令转换为微指令。命令微指令指导微处理器加载第二输入文本块，并且在指示微处理器存储对应于第一输入文本块的输出文本块之前对第二输入文本块执行加密操作之一。因此，输出文本块在对第二输入文本块的密码操作之一的执行期间被存储。

79. 发明申请

US20050099841A1 Networked processor for a pipeline architecture 有权
标题翻译：用于管道架构的网络处理器
公开(公告)号：US20050099841A1
公开(公告)日：2005-05-12
申请号：US10726470
申请日：2003-12-02
申请人： Shridhar Mukund , Mahesh Gopalan , Neeraj Kashalkar
发明人： Shridhar Mukund , Mahesh Gopalan , Neeraj Kashalkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/315 , G11C11/00
CPC分类号： G06F9/30025 , G06F9/30007 , G06F9/3001 , G06F9/30032
摘要： A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.
摘要翻译：提供了网络应用处理器。处理器包括被配置为接收数据分组的输入套接字。处理器包括用于保存指令的存储器和被配置为访问与处理级相关联的数据结构的电路。被配置为访问数据结构的电路使得能够从存储器单元访问单个操作数。提供了算术逻辑单元（ALU）。包括用于对准由ALU处理的操作数的电路。用于对准操作数的电路使得操作数被最低有效位对准，其中用于对准操作数的电路向操作数提供扩展以允许ALU处理不同大小的操作数。

80. 发明申请

US20040255130A1 Microprocessor apparatus and method for providing configurable cryptographic key size 有权
标题翻译：用于提供可配置密码密钥大小的微处理器装置和方法
公开(公告)号：US20040255130A1
公开(公告)日：2004-12-16
申请号：US10826632
申请日：2004-04-16
申请人： VIA Technologies Inc.
发明人： G. Glenn Henry , Thomas A. Crispin , Timothy A. Elliott , Terry Parks
IPC分类号： H04L009/00
CPC分类号： G06F21/72 , G06F9/30007 , H04L9/0631 , H04L9/0637 , H04L9/12 , H04L2209/125 , H04L2209/24
摘要： The present invention provides an apparatus and method for performing cryptographic operations. In one embodiment, an apparatus is provided for performing cryptographic operations. The apparatus includes a cryptographic instruction, keygen logic, and execution logic. The cryptographic instruction is received by a computing device as part of an instruction flow executing on the computing device. The cryptographic instruction prescribes one of the cryptographic operations, and also prescribes that a provided cryptographic key be expanded into a corresponding key schedule for employment during execution of the one of the cryptographic operations. The keygen logic is operatively coupled to the cryptographic instruction. The keygen logic directs the computing device to expand the provided cryptographic key into the corresponding key schedule. The execution logic is coupled to the keygen logic. The execution logic expands the provided cryptographic key into the corresponding key schedule.
摘要翻译：本发明提供了一种用于执行密码操作的装置和方法。在一个实施例中，提供了一种用于执行加密操作的装置。该装置包括密码指令，密钥生成逻辑和执行逻辑。密码指令由计算设备接收，作为在计算设备上执行的指令流的一部分。加密指令规定了一个加密操作，并且还规定所提供的密码密钥在执行该密码操作之一期间被扩展为对应的密钥调度表。密钥生成逻辑可操作地耦合到密码指令。密钥生成逻辑指示计算设备将提供的加密密钥扩展到相应的密钥调度表中。执行逻辑与keygen逻辑耦合。执行逻辑将提供的加密密钥扩展到相应的密钥调度表中。

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