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71. 发明授权

US08984041B2 Performing arithmetic operations using both large and small floating point values 有权
标题翻译：使用大和小浮点值执行算术运算
公开(公告)号：US08984041B2
公开(公告)日：2015-03-17
申请号：US13598847
申请日：2012-08-30
申请人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
发明人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F7/38 , G06F7/483
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译：提供了用于在数据处理系统中执行浮点算术运算的机构。接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值，至少一个浮点操作数的尾数的位的范围。基于向量值和多个浮点操作数，生成用于浮点运算的结果值。

72. 发明授权

US08959131B2 Number format pre-conversion instructions 有权
标题翻译：数字格式转换前说明
公开(公告)号：US08959131B2
公开(公告)日：2015-02-17
申请号：US13137950
申请日：2011-09-22
申请人： Jorn Nystad , Andreas Due Engh-Halstvedt , Simon Alex Charles
发明人： Jorn Nystad , Andreas Due Engh-Halstvedt , Simon Alex Charles
IPC分类号： G06F7/38 , G06F7/483 , G06F7/499
CPC分类号： G06F5/00 , G06F7/483 , G06F7/499 , G06F7/49963 , G06F9/30014 , G06F9/30025 , G06F2207/382 , H03M7/24
摘要： Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantize and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.
摘要翻译：用于处理数据的装置包括用于解码程序指令的处理电路16,18,20,22,24,26和解码器电路14。所解码的程序指令包括一个浮点预转换指令，其执行圆到最近的连接，以便在输入浮点数的尾数字上偶数舍入以产生具有相同尾数长度但尾数四舍五入的输出浮点数对应于较短的尾数字段的位置。输出尾数字段包括将值的后缀连接在舍入值上。用于电路14的解码器还响应于整数预转换指令来量化和输入整数值，使用到最近的连带到偶数舍入以形成输出整数操作数，其具有匹配到的尾数大小的有效位数使用整数到浮点转换指令后续整数的浮点数。

73. 发明申请

US20150026227A1 Block Exponent Integer Data Format 审中-公开
标题翻译：块指数整数数据格式
公开(公告)号：US20150026227A1
公开(公告)日：2015-01-22
申请号：US13943162
申请日：2013-07-16
申请人： Lai Xu , Ismail Lakkis , Yacoub Hirbawi
发明人： Lai Xu , Ismail Lakkis , Yacoub Hirbawi
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/38
摘要： A digital processing system comprises an input configured for receiving data in block exponent integer format, wherein each block comprises a plurality of data values sharing a single exponent. The plurality of data values has a common data bit width, and the exponent has an exponent bit width. An arithmetic processor performs arithmetic operations on the input data to produce output data in block exponent integer format. The arithmetic processor comprises a format optimizer for reducing at least one of the data bit width and the exponent bit width prior to performing arithmetic operations. The bit width is reduced to improve system power efficiency while meeting a predetermined target system performance.
摘要翻译：数字处理系统包括被配置为以块指数整数格式接收数据的输入，其中每个块包括共享单个指数的多个数据值。多个数据值具有公共数据位宽度，并且指数具有指数位宽度。算术处理器对输入数据执行算术运算，以块指数整数格式产生输出数据。算术处理器包括格式优化器，用于在执行算术运算之前减少数据位宽度和指数位宽度中的至少一个。减小位宽以提高系统功率效率，同时满足预定的目标系统性能。

74. 发明授权

US08930432B2 Floating point execution unit with fixed point functionality 有权
标题翻译：具有固定点功能的浮点执行单元
公开(公告)号：US08930432B2
公开(公告)日：2015-01-06
申请号：US13197894
申请日：2011-08-04
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F7/38 , G06F7/44
CPC分类号： G06F9/30014 , G06F7/483 , G06F9/3001 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3836 , G06F9/3889 , G06F2207/3824
摘要： A floating point execution unit is capable of selectively repurposing one or more adders in an exponent path of the floating point execution unit to perform fixed point addition operations, thereby providing fixed point functionality in the floating point execution unit.
摘要翻译：浮点执行单元能够选择性地重新排列浮点执行单元的指数路径中的一个或多个加法器，以执行固定点加法运算，从而在浮点执行单元中提供固定点功能。

75. 发明授权

US08914430B2 Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions 有权
标题翻译：增加功能单元，能够执行刻度，圆形，GETEXP，圆形，GETMANT，缩小，范围和类指令
公开(公告)号：US08914430B2
公开(公告)日：2014-12-16
申请号：US12890543
申请日：2010-09-24
申请人： Amit Gradstein , Cristina S. Anderson , Zeev Sperber , Simon Rubanovich , Benny Eitan
发明人： Amit Gradstein , Cristina S. Anderson , Zeev Sperber , Simon Rubanovich , Benny Eitan
IPC分类号： G06F7/38 , G06F9/38 , G06F9/30
CPC分类号： G06F7/57 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F9/3893
摘要： A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
摘要翻译：描述了涉及用功能单元执行第一指令的方法。第一条指令是乘法加法指令。该方法还包括执行与功能单元的第二指令。第二个指令是一个圆形指令。

76. 发明授权

US08903881B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 有权
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08903881B2
公开(公告)日：2014-12-02
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42 , G06F7/483 , G06F7/499
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数偏移由移位量产生单元生成的移位量而获得的量化尾数的移位单元和用于存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

77. 发明申请

US20140351309A1 FMA UNIT, IN PARTICULAR FOR UTILIZATION IN A MODEL COMPUTATION UNIT FOR PURELY HARDWARE-BASED COMPUTING OF FUNCTION MODELS 有权
标题翻译： FMA单位，特别是在用于基于硬件的功能模型计算的模型计算单元中的应用
公开(公告)号：US20140351309A1
公开(公告)日：2014-11-27
申请号：US14283528
申请日：2014-05-21
申请人： Wolfgang FISCHER , Andre GUNTORO
发明人： Wolfgang FISCHER , Andre GUNTORO
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： An FMA unit, for carrying out an arithmetic operation in a model computation unit of a control unit, is configured to process input of two factors and one summand in the form of floating point values, and provide a computation result of such processing as an output variable in the form of a floating point value. The FMA unit is designed to carry out a multiplication and a subsequent addition, the bit resolutions of the inputs for the factors being lower than the bit resolution of the input for the summand and the bit resolution of the output variable.
摘要翻译：用于在控制单元的模型计算单元中执行算术运算的FMA单元被配置为以浮点值的形式处理两个因子和一个求和的输入，并且提供诸如输出的处理的计算结果变量以浮点值的形式。 FMA单元被设计为执行乘法和后续加法，因子的输入的比特分辨率低于求和的输入的比特分辨率和输出变量的比特分辨率。

78. 发明授权

US08874630B2 Apparatus and method for converting data between a floating-point number and an integer 有权
标题翻译：用于在浮点数和整数之间转换数据的装置和方法
公开(公告)号：US08874630B2
公开(公告)日：2014-10-28
申请号：US13101356
申请日：2011-05-05
申请人： Hyeong-Seok Yu , Suk-Jin Kim , Sang-Su Park , Yong-Surk Lee
发明人： Hyeong-Seok Yu , Suk-Jin Kim , Sang-Su Park , Yong-Surk Lee
IPC分类号： G06F7/00 , G06F7/483 , H03M7/24
CPC分类号： G06F7/483 , H03M7/24
摘要： An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.
摘要翻译：提供了一种用于在浮点数和整数之间转换数据的装置和方法。该装置包括：数据转换器，被配置为基于输入二进制数据的符号和输出格式确定输入二进制数据的符号和输出格式，转换输入的二进制数据并将输入的二进制数据转换为补码数据，偏置值发生器，被配置为基于输入二进制数据的舍入模式来确定输入的二进制数据是否已被舍入，并相应地生成偏差值; 以及加法器，被配置为通过将所述补码和偏置值相加来将输入的二进制数据转换成二进制补码。

79. 发明授权

US08862650B2 Calculation of trigonometric functions in an integrated circuit device 有权
标题翻译：集成电路设备中三角函数的计算
公开(公告)号：US08862650B2
公开(公告)日：2014-10-14
申请号：US13288685
申请日：2011-11-03
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/38 , G06F7/548 , G06F1/03 , G06F1/035 , G06F7/483
CPC分类号： G06F7/548 , G06F1/03 , G06F1/035 , G06F7/483 , G06F2101/04
摘要： Circuitry for computing a tangent function of an input value includes first look-up table circuitry that stores pre-calculated tangent values of a limited number of sample values, circuitry for inputting bits of the input value of most significance as inputs to the first look-up table circuitry to look up one of the pre-calculated tangent values as a first intermediate tangent value, circuitry for calculating a second intermediate tangent value from one or more ranges of remaining bits of the input value, and circuitry for combining the first intermediate tangent value and the second intermediate tangent value to yield the tangent function of the input value.
摘要翻译：用于计算输入值的切线函数的电路包括第一查询表电路，其存储有限数量的采样值的预先计算的切线值，用于输入最重要的输入值的位的电路用作第一查找表的输入，查找预先计算的正切值中的一个作为第一中间切线值的电路，用于从输入值的剩余位的一个或多个范围计算第二中间切线值的电路，以及用于组合第一中间切线值和第二中间切线值，以产生输入值的切线函数。

80. 发明申请

US20140280425A1 METHOD AND DEVICE FOR GENERATING AN EXCEPTION 有权
标题翻译：用于产生异常的方法和设备
公开(公告)号：US20140280425A1
公开(公告)日：2014-09-18
申请号：US13841630
申请日：2013-03-15
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49905
摘要： A floating point value can represent a number or something that is not a number (NaN). A floating point value that is a NaN having data field that stores information, such as a propagation count that indicates the number of times a NaN value has been propagated through instructions. A NaN evaluation instruction can determine whether one or more operands is a NaN operand of a particular type, and if so can generate a result that is a NaN of a different type. An exception can be generated based upon the NaN of the different type being provided as a resultant
摘要翻译：浮点值可以表示数字或不是数字（NaN）的数据。具有存储信息的数据字段的NaN的浮点值，例如表示通过指令传播NaN值的次数的传播计数。 NaN评估指令可以确定一个或多个操作数是否是特定类型的NaN操作数，如果可以生成作为不同类型的NaN的结果。可以基于作为结果提供的不同类型的NaN产生异常

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