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1. 发明授权

US08903881B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 有权
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08903881B2
公开(公告)日：2014-12-02
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42 , G06F7/483 , G06F7/499
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数偏移由移位量产生单元生成的移位量而获得的量化尾数的移位单元和用于存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

2. 发明授权

US08788561B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 失效
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08788561B2
公开(公告)日：2014-07-22
申请号：US13441020
申请日：2012-04-06
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/483 , G06F7/49942
摘要： An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.
摘要翻译：算术电路计算通过两个值的加减运算获得的并以预定的固定精度表示的值的校正值。

3. 发明申请

US20120259906A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 失效
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259906A1
公开(公告)日：2012-10-11
申请号：US13441020
申请日：2012-04-06
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/483 , G06F7/49942
摘要： An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.
摘要翻译：算术电路计算通过两个值的加减运算获得的并以预定的固定精度表示的值的校正值。

4. 发明申请

US20120259903A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 审中-公开
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259903A1
公开(公告)日：2012-10-11
申请号：US13439932
申请日：2012-04-05
申请人： Ryuji KAN , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji KAN , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/49957
摘要： An arithmetic circuit for rounding pre-rounded data includes a first register to store first-format pre-rounded data that includes a mantissa of a fixed-precision floating-point number using a base-N numbering system, and includes an exponent for the mantissa, a second register to store rounding precision data indicative of precision for rounding the pre-rounded data, a leading zero counting unit to count consecutive zeros starting from a most significant bit of the mantissa stored in the first register, an exponent generating unit to generate a post-round exponent indicative of an exponent for a rounded significant by subtracting the number of zeros counted by the leading zero counting unit and the rounding precision data from a sum of one and the exponent stored in the first register, and an output register to store the post-round exponent and a rounding-add value that is to be added to a digit at which rounding is performed.
摘要翻译：用于舍入前置数据的算术电路包括：第一寄存器，用于存储使用基本N编号系统的包括固定精度浮点数的尾数的第一格式的前置数据，并且包括用于尾数的指数第二寄存器，用于存储指示用于舍入预舍数据的精度的舍入精度数据;前导零计数单元，用于从存储在第一寄存器中的尾数的最高有效位开始计数连续零;指数生成单元，用于生成指示通过从前导零计数单元计数的零的数目和来自存储在第一寄存器中的一个和的指数的舍入精度数据的舍入精度数据来指示舍入有效的指数的后向指数，以及输出寄存器存储后轮指数和要添加到执行舍入的数字的舍入加法值。

5. 发明授权

US07971029B2 Barrier synchronization method, device, and multi-core processor 有权
标题翻译：屏障同步方法，设备和多核处理器
公开(公告)号：US07971029B2
公开(公告)日：2011-06-28
申请号：US12638746
申请日：2009-12-15
申请人： Hideyuki Unno , Masaki Ukai , Matthew Depetro
发明人： Hideyuki Unno , Masaki Ukai , Matthew Depetro
IPC分类号： G06F15/177 , G06F15/76
CPC分类号： G06F9/52 , G06F9/522
摘要： A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.
摘要翻译：用于实现多个处理器核心中属于同一同步组的至少2个处理器核心的屏障同步的屏障同步装置包括在具有多个处理器核心的多核处理器中，并且当该处理器核心中的两个或多个处理器核心多核处理器属于同一同步组，所包含的屏障同步装置用于实现屏障同步。

6. 发明申请

US20130262808A1 COMPRESSION AND DECOMPRESSION SYSTEM, COMPRESSION APPARATUS, DECOMPRESSION APPARATUS AND COMPRESSION AND DECOMPRESSION METHOD 审中-公开
标题翻译：压缩和分解系统，压缩装置，分解装置和压缩和分解方法
公开(公告)号：US20130262808A1
公开(公告)日：2013-10-03
申请号：US13611804
申请日：2012-09-12
申请人： Hideyuki Unno
发明人： Hideyuki Unno
IPC分类号： H03M7/40 , G06F12/02
CPC分类号： H03M7/3086 , H03M7/702
摘要： In a compression and decompression system that performs data compression and decompression, the decompression of compressed data is performed in a way that a compression apparatus generates a byte code string as compressed data, and a decompression apparatus executes the byte code string. The byte code includes an 8-byte-unit copy instruction and direct data processing instruction, and the compression apparatus determines whether to use the 8-byte-unit copy instruction and direct data processing instruction or a byte-unit copy instruction and direct data processing instruction upon decompression, and generates the byte code.
摘要翻译：在执行数据压缩和解压缩的压缩和解压缩系统中，压缩数据的解压缩以压缩装置产生字节码串作为压缩数据的方式执行，解压装置执行字节码串。字节代码包括8字节单元复制指令和直接数据处理指令，并且压缩装置确定是使用8字节单元复制指令和直接数据处理指令还是使用字节单元复制指令和直接数据处理指令解压缩，并生成字节码。

7. 发明申请

US20090064153A1 COMMAND SELECTION METHOD AND ITS APPARATUS, COMMAND THROW METHOD AND ITS APPARATUS 失效
标题翻译：命令选择方法及其设备，命令方法及其设备
公开(公告)号：US20090064153A1
公开(公告)日：2009-03-05
申请号：US12199447
申请日：2008-08-27
申请人： Naoya ISHIMURA , Hideyuki Unno
发明人： Naoya ISHIMURA , Hideyuki Unno
IPC分类号： G06F9/46 , G06F9/38 , G06F9/315
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/5011 , G06F2209/5021 , G06F2209/507
摘要： When selecting one command within a processor from a plurality of command queues vested with order of priority, the order of priority assigned to the plurality of command queues is dynamically changed so as to select a command, on a priority basis, from a command queue vested with a higher priority from among the plurality of command queues in accordance with the post-change order of priority.
摘要翻译：当从多个以优先级顺序赋予的命令队列中选择一个命令时，分配给多个命令队列的优先级顺序被动态地改变，从而优先地从命令队列中选择一个命令根据优先级的改变后顺序，从多个命令队列中具有较高的优先级。

8. 发明授权

US08301969B2 Control method of information processing device and information processing device 失效
标题翻译：信息处理装置和信息处理装置的控制方法
公开(公告)号：US08301969B2
公开(公告)日：2012-10-30
申请号：US12198577
申请日：2008-08-26
申请人： Hideyuki Unno , Masaki Ukai , Naozumi Aoki
发明人： Hideyuki Unno , Masaki Ukai , Naozumi Aoki
IPC分类号： H03M13/00
CPC分类号： H04L1/0042 , G06F11/349 , H04L1/0047 , H04L25/4915
摘要： A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).
摘要翻译：发送侧设备（10）和接收侧设备（20）经由包括TAG位（31），数据位（32）和错误检测/校正ECC位（33）的总线（30）彼此连接。发送侧装置（10）使用冗余比特反相电路（14）反相对应于触发信号（41和42）的ECC比特（33）的不同比特。在接收侧设备（20）中，从错误检测/校正电路（22）接收到错误报告信号（26）的确定电路（24）从ECC位中的错误位的位置确定（33），所述触发信号（41和42）中的哪一个已经从所述发送侧装置（10）发送。

9. 发明授权

US08196028B2 Error detection device 失效
标题翻译：错误检测装置
公开(公告)号：US08196028B2
公开(公告)日：2012-06-05
申请号：US12200390
申请日：2008-08-28
申请人： Hideyuki Unno
发明人： Hideyuki Unno
IPC分类号： H03M13/00
CPC分类号： G06F11/073 , G06F11/0763 , G06F11/10 , G06F12/0802
摘要： A data buffer control unit obtains data from a cache according to a command retained in a command queue retaining a command(s) for reading data from the cache, and a magic ID generation circuit generates a magic ID. The data buffer control unit assigns the data obtained from the cache with the magic ID, writes the assigned data to a data buffer, and returns the magic ID to the command queue. When the data buffer control unit receives a read request and the magic ID which is returned to the command queue, it reads the data, which corresponds to the read request, from the command queue and compares the magic ID assigned in the read data and the received magic ID. If the two magic IDs compared by the data buffer control unit are not identical, a packet generator detects an error and reports the error to a host.
摘要翻译：数据缓冲器控制单元根据保存在用于从高速缓存读取数据的命令的命令队列中保留的命令从高速缓存获取数据，并且魔术ID生成电路生成魔术ID。数据缓冲器控制单元将从缓存获得的数据分配给魔术ID，将分配的数据写入数据缓冲器，并将魔术ID返回到命令队列。当数据缓冲器控制单元接收到读取请求和返回到命令队列的魔术ID时，它从命令队列中读取与读取请求对应的数据，并将读取的数据中分配的魔术ID和收到魔法ID。如果由数据缓冲器控制单元比较的两个魔术ID不相同，则分组生成器检测到错误并向主机报告错误。

10. 发明授权

US08161274B2 Command selection method and its apparatus 失效
标题翻译：命令选择方法及其装置
公开(公告)号：US08161274B2
公开(公告)日：2012-04-17
申请号：US12199447
申请日：2008-08-27
申请人： Naoya Ishimura , Hideyuki Unno
发明人： Naoya Ishimura , Hideyuki Unno
IPC分类号： G06F9/48 , G06F9/52 , G06F13/362 , G06F13/368
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/5011 , G06F2209/5021 , G06F2209/507
摘要： When selecting one command within a processor from a plurality of command queues vested with order of priority, the order of priority assigned to the plurality of command queues is dynamically changed so as to select a command, on a priority basis, from a command queue vested with a higher priority from among the plurality of command queues in accordance with the post-change order of priority.
摘要翻译：当从多个以优先级顺序赋予的命令队列中选择一个命令时，分配给多个命令队列的优先级顺序被动态地改变，从而优先地从命令队列中选择一个命令根据优先级的改变后顺序，从多个命令队列中具有较高的优先级。

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