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1. 发明申请

US20110298788A1 PERFORMING VECTOR MULTIPLICATION 有权
标题翻译：执行矢量多项式
公开(公告)号：US20110298788A1
公开(公告)日：2011-12-08
申请号：US12794207
申请日：2010-06-04
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06F7/483 , G06F7/5443
摘要： A method includes receiving packed data corresponding to pixel components to be processed at a graphics pipeline. The method includes unpacking the packed data to generate floating point numbers that correspond to the pixel components. The method also includes routing each of the floating point numbers to a separate lane of the graphics pipeline. Each of the floating point numbers are to be processed by multiplier units of the graphics pipeline.
摘要翻译：一种方法包括在图形流水线处接收对应于要处理的像素分量的打包数据。该方法包括打包打包数据以产生对应于像素分量的浮点数。该方法还包括将每个浮点数路由到图形流水线的单独通道。每个浮点数由图形管线的乘法器单元处理。

2. 发明授权

US08412980B2 Fault tolerant stability critical execution checking using redundant execution pipelines 失效
标题翻译：使用冗余执行管道的容错稳定性关键执行检查
公开(公告)号：US08412980B2
公开(公告)日：2013-04-02
申请号：US12794256
申请日：2010-06-04
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F11/16 , G06F11/00
CPC分类号： G06F11/0751 , G06F9/30185 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F11/1641 , G06F2201/845
摘要： A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.
摘要翻译：电路布置和方法利用处理单元中的现有冗余执行流水线并行执行稳定性关键指令的多个实例，从而可以比较指令的多个实例的结果以便检测错误。对于不需要或不需要容错或稳定性关键执行的其他类型的指令，以更传统的方式利用冗余执行流水线，使多个非稳定性关键指令同时发布到冗余执行管线并由其执行。因此，对于非稳定性关键程序代码，保留具有多个冗余执行单元的性能优点，但是在需要对某些程序代码进行容错或稳定性关键执行的情况下，冗余执行单元可以重新利用以提供对这种指令的无故障执行的更大保证。

3. 发明申请

US20110302450A1 FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDANT EXECUTION PIPELINES 失效
标题翻译：使用冗余执行管道的故障稳定性关键执行检查
公开(公告)号：US20110302450A1
公开(公告)日：2011-12-08
申请号：US12794256
申请日：2010-06-04
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F11/07 , G06F11/14
CPC分类号： G06F11/0751 , G06F9/30185 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F11/1641 , G06F2201/845
摘要： A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.
摘要翻译：电路布置和方法利用处理单元中的现有冗余执行流水线并行执行稳定性关键指令的多个实例，从而可以比较指令的多个实例的结果以便检测错误。对于不需要或不需要容错或稳定性关键执行的其他类型的指令，以更传统的方式利用冗余执行流水线，使多个非稳定性关键指令同时发布到冗余执行管线并由其执行。因此，对于非稳定性关键程序代码，保留具有多个冗余执行单元的性能优点，但是在需要对某些程序代码进行容错或稳定性关键执行的情况下，冗余执行单元可以重新利用以提供对这种指令的无故障执行的更大保证。

4. 发明授权

US08880852B2 Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address 有权
标题翻译：基于操作码和操作数检测逻辑上的非有效操作，并设置标志将后续指令中指定的地址解码为不同的地址
公开(公告)号：US08880852B2
公开(公告)日：2014-11-04
申请号：US13281958
申请日：2011-10-26
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/318 , G06F9/00 , G06F9/30 , G06F9/34
CPC分类号： G06F9/00 , G06F9/30145 , G06F9/3016 , G06F9/30178 , G06F9/30181 , G06F9/34
摘要： A method, apparatus, and program product execute instructions of an instruction stream and detect logically non-significant operations in the instruction stream. Then, based on that detection, a target or source address of a subsequent instruction is adjusted. In some instances, doing so enables a greater number of addresses, e.g., registers, to be accessed in a given number of bit positions within an instruction format.
摘要翻译：方法，装置和程序产品执行指令流的指令并且检测指令流中的逻辑上非有效操作。然后，基于该检测，调整后续指示的目标或源地址。在一些情况下，这样做使得能够在指令格式中的给定数量的位位置中访问更多数量的地址，例如寄存器。

5. 发明授权

US08522254B2 Programmable integrated processor blocks 失效
标题翻译：可编程集成处理器模块
公开(公告)号：US08522254B2
公开(公告)日：2013-08-27
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F3/00 , G06F15/00
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译：芯片上的网络的集成处理器块可编程以执行第一功能。集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问到片上存储器。

6. 发明申请

US20120084535A1 Opcode Space Minimizing Architecture Utilizing Instruction Address to Indicate Upper Address Bits 有权
标题翻译：操作码空间最小化使用指令地址来指示上位地址的架构
公开(公告)号：US20120084535A1
公开(公告)日：2012-04-05
申请号：US12894697
申请日：2010-09-30
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/3016 , G06F9/30181 , G06F9/345 , G06F9/3824
摘要： Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the upper address bits of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.
摘要翻译：由于现代微处理器内核中的寄存器数量和新指令的数量不断增加，指令编码中存在的地址宽度不断扩大，更少的指令操作码可用，使得更难于将现有架构的新指令添加到现有的架构中，而无需使用不正当的具有诸如源破坏性操作等缺点的技巧。所公开的发明利用专门的解码和地址计算硬件，其将指令地址的固定数目的最低有效位连接到包含在指令中的每个寄存器地址部分的高地址位，从而产生完整寄存器地址，而不是提供完整寄存器指令中使用的每个寄存器的地址宽度。这释放了其他指令的有价值的操作码空间，避免了编译器的复杂性。这很好地与汇编语言中大多数循环展开的方式保持一致，独立操作在内存中彼此靠近。

7. 发明申请

US20110321049A1 Programmable Integrated Processor Blocks 失效
标题翻译：可编程集成处理器模块
公开(公告)号：US20110321049A1
公开(公告)日：2011-12-29
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/46 , G06F9/318
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译：芯片上的网络的集成处理器块可编程以执行第一功能。集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问到片上存储器。

8. 发明授权

US10261793B2 Instruction predication using instruction address pattern matching 有权
公开(公告)号：US10261793B2
公开(公告)日：2019-04-16
申请号：US13328185
申请日：2011-12-16
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/30
摘要： A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses.

9. 发明授权

US09195463B2 Processing core with speculative register preprocessing in unused execution unit cycles 有权
标题翻译：在未使用的执行单位周期内处理具有推测寄存器预处理的内核
公开(公告)号：US09195463B2
公开(公告)日：2015-11-24
申请号：US13307575
申请日：2011-11-30
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/302 , G06F9/38 , G06F7/499 , G06F9/30
CPC分类号： G06F9/383 , G06F7/499 , G06F9/30014 , G06F9/30025 , G06F9/3836 , G06F9/384 , G06F9/3875 , G06F9/3885
摘要： A method and circuit arrangement speculatively preprocess data stored in a register file during otherwise unused cycles in an execution unit, e.g., to prenormalize denormal floating point values stored in a floating point register file, to decompress compressed values stored in a register file, to decrypt encrypted values stored in a register file, or to otherwise preprocess data that is stored in an unprocessed form in a register file.
摘要翻译：一种方法和电路装置在执行单元中的其他未使用的周期期间推测性地预处理存储在寄存器文件中的数据，例如，将存储在浮点寄存器文件中的非正常浮点值预正规化，以解压缩存储在寄存器堆中的压缩值，以解密存储在寄存器文件中的加密值，或以其他方式预处理以未处理形式存储在寄存器文件中的数据。

10. 发明授权

US09075599B2 Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bits 有权
标题翻译：操作码空间最小化结构，利用指令地址的最低有效部分作为高位寄存器地址位
公开(公告)号：US09075599B2
公开(公告)日：2015-07-07
申请号：US12894697
申请日：2010-09-30
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/345 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30098 , G06F9/3016 , G06F9/30181 , G06F9/345 , G06F9/3824
摘要： Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the most significant side of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.
摘要翻译：由于现代微处理器内核中的寄存器数量和新指令的数量不断增加，指令编码中存在的地址宽度不断扩大，更少的指令操作码可用，使得更难于将现有架构的新指令添加到现有的架构中，而无需使用不正当的具有诸如源破坏性操作等缺点的技巧。所公开的发明利用专门的解码和地址计算硬件，其将指令地址的固定数量的最低有效位连接到包含在指令中的每个寄存器地址部分的最高有效侧，从而产生完整寄存器地址，而不是提供完整寄存器指令中使用的每个寄存器的地址宽度。这释放了其他指令的有价值的操作码空间，避免了编译器的复杂性。这很好地与汇编语言中大多数循环展开的方式保持一致，独立操作在内存中彼此靠近。

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